Electronics Forum: defect (Page 12 of 226)

Black pad defect

Electronics Forum | Thu Mar 27 14:49:20 EST 2003 | MA/NY DDave

Hi Enrique, I don't remember all the energy levels that make the techniques you or your associates are using, effective. Each energy level yields information that must be understood is the best that I should give. HEY Based on my comment, does this

Solder defect problem.

Electronics Forum | Mon Dec 01 15:21:08 EST 2003 | davef

Hey, I thought you were in the BIG house on some trumped-up tax rap. We use many RF shields each month. Generally, the shields are not plated and made of alloy 770 (or alloy 752), half hard temper, as the base material. * Alloy 770; 55%Cu, 27%Zn,

LED lifted soldering defect

Electronics Forum | Wed Dec 04 08:15:55 EST 2019 | proceng1

You have a peak of 216 and roughly 40 seconds TAL. So you are right in the middle of the given ranges. So there's room to get things a little hotter and for a little longer. I am surprised you are having this trouble with TIN/ LEAD, as the process

LED lifted soldering defect

Electronics Forum | Wed Dec 04 10:59:04 EST 2019 | dwl

The solder looks a little grainy for Sn/Pb solder but that might just be the picture quality. There appears to be plenty of solder on the pads, so I'd rule out anything to do with the stencil. One possibility that springs to mind; how long is your

LED lifted soldering defect

Electronics Forum | Wed Dec 04 16:31:23 EST 2019 | kylehunter

Hmm, OK thanks for the input guys. Yeah, I'm surprised because our profile seems pretty solid, and it is such an isolated issue. I like the thought of the flux drying out as a potential cause. It was definitely exposed to the air, and while we tried

TOMBSTONE defect Redution suggestion.

Electronics Forum | Sun Sep 06 03:24:31 EDT 2020 | rsatmech

Hi All, We are frequently getting tombstone in an induction component. (0102) There is no paste offset or placement offset. PCB pad design is not as per recommendation. Stencil opening is 1:1 Same part used in two locations and both the locati

TOMBSTONE defect Redution suggestion.

Electronics Forum | Tue Sep 08 15:12:56 EDT 2020 | cyber_wolf

I concur with Spoilt on all accounts. If the tombstones are isolated to the same P/N this is an indicator that your process is probably not to blame. At this point you have to try and mitigate the issue. Things to try [if possible] : 1. Try a soa

TOMBSTONE defect Redution suggestion.

Electronics Forum | Fri Sep 11 15:58:50 EDT 2020 | majdi4

You haven't communicated what thickness of stencil you are working with ... it's interesting to know..at first, you need to reduce the amount of CAB deposited because with 1X1 stencil aperture size you are depositing an amount important CAB .. so, I

Black pad defect

Electronics Forum | Tue Feb 11 22:28:25 EST 2003 | davef

What do you mean by "new information"? On final module testing: * If you have hypercorroded nickel and you detect it during final testing, you'll notice it. * If you have hypercorroded nickel and you don't detect it during final testing, you'll ship

LED lifted soldering defect

Electronics Forum | Wed Dec 04 04:28:58 EST 2019 | oxygensmd

It seems there isn't right connection between solder and solder-legs. Maybe check that the LEDs get huminidity, have some oxidation on the legs, try different solder paste, check the reflow solder profile. On the photo I can not saw properly reflowe


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