Technical Library | 1999-05-07 09:58:23.0
From the point of view of an operating system, a computer is managed and optimized in terms of the application programming model and the management of system resources. For the TFLOPS system, the problem is to manage and optimize large scale parallelism. This paper looks at the management in terms of three key topics: memory management, communication, and input/output.
Technical Library | 2013-03-04 16:51:00.0
Chip-scale (or chip-size) packages are rapidly becoming an important element in electronics due to their size, performance, and cost advantages [Hou, 1998]. The Chip Scale Package (CSP) is becoming a key semiconductor package type, particularly for consumer products. Due to their relatively smaller size, new challenges are presented in the rework and repair of CSPs. (...) The specific focus of this paper is the removal process for rework of CSPs and the site scavenging methods required to properly prepare the circuit board for a new component. Process factors such as the heating, fluxing and, atmosphere are discussed.
Technical Library | 2023-03-13 19:12:56.0
Printed electronics (PE) is impacting almost every branch of manufacturing. The printing of electronics on mechanically flexible substrates such as plastic, paper and textile, using traditional printing techniques, provides novel applications for wearable and stretchable electronics. Government sponsored consortiums, universities, contract printers, startups and global manufacturers are developing processes to bring this technology to market faster, more costeffectively and at scale. By increasing the speed of technology adoption while following industrialization best practices, industry researchers aim to create processes that ramp up the scale of production for simple circuits and integrated conductive structures.
Technical Library | 2006-10-02 14:26:47.0
This paper addresses the assembly and reliability of 0.5 mm pitch leadless Chip Scale Packages (CSP) on .062" immersion Ag plated printed circuit boards (PCB) using Pb-free solder paste. Four different leadless CSP designs were studied and each was evaluated using multiple PCB attachment pad designs.
Technical Library | 2017-03-02 18:13:05.0
The need for more energy-efficient solid-state switches beyond complementary metal-oxide-semiconductor (CMOS) transistors has become a major concern as the power consumption of electronic integrated circuits (ICs) steadily increases with technology scaling. Nano-Electro-Mechanical (NEM) relays control current flow by nanometer-scale motion to make or break physical contact between electrodes, and offer advantages over transistors for low-power digital logic applications: virtually zero leakage current for negligible static power consumption; the ability to operate with very small voltage signals for low dynamic power consumption; and robustness against harsh environments such as extreme temperatures. Therefore, NEM logic switches (relays) have been investigated by several research groups during the past decade. Circuit simulations calibrated to experimental data indicate that scaled relay technology can overcome the energy-efficiency limit of CMOS technology. This paper reviews recent progress toward this goal, providing an overview of the different relay designs and experimental results achieved by various research groups, as well as of relay-based IC design principles. Remaining challenges for realizing the promise of nano-mechanical computing, and ongoing efforts to address these, are discussed.
Technical Library | 2015-09-03 18:06:11.0
While the density of chip-to-chip and chip-to-package component interconnections increases and their size decreases the ease of manufacture and the interconnection reliability are being reduced. This paper will introduce the use of embedded fibers in the interconnections as a means of addressing these issues.
Technical Library | 1999-05-07 08:48:52.0
This paper describes how the quality and reliability of Intel's products are designed, measured, modeled, and maintained. Four main reliability topics: ESD protection, electromigration, gate oxide wearout, and the modeling and management of mechanical stresses are discussed. Based on an analysis of the reliability implications of device scaling, we show how these four topics are of prime importance to component reliability...
Technical Library | 2007-07-12 14:29:37.0
Over the last ten years, there have been a large number of publications describing work into lead free electronics soldering. They have come from all regions of the world and from academic organisations, individual companies and consortia. Although a number of these studies have culminated in "production trials", these have invariably been on a limited scale and they were essentially a demonstration, rather than the first step to implementation.
Technical Library | 2008-01-16 18:25:55.0
The consumer's interest for smaller, lighter and higher performance electronics products has increased the use of ultra fine pitch packages, such as Flip Chips and Chip Scale Packages, in printed circuit board (PCB) assembly. The assembly processes for these ultra fine pitch packages are extremely complex and each step in the assembly process influences the assembly yield and reliability.
Technical Library | 2018-08-01 11:25:59.0
With complexities of PCB design scaling and manufacturing processes adopting to environmentally friendly practices raise challenges in ensuring structural quality of PCBs. This makes it essential to have a good 'Design for Test' (DFT) to ensure a robust structural test. (...)During the course of the DFT review, can we realize a good test strategy for the PCBA. How can the test strategy of the PCBA be partitioned as to what portions of the design can be covered structurally and what is covered functionally, in a way that provides best diagnostics to discover faults
