Technical Library | 2014-03-27 14:50:01.0
Because of the phase out of CFC's and HCFC's, standard solder pastes and fluxes evolved from RA and RMA fluxes, to No-Clean, to low residue No-Clean, to very low residue No-Clean. Many companies came out with their cleaning solutions, aqueous and semi-aqueous, with each product release being more innovative than the previous one. Unfortunately for most of the suppliers of cleaners, two other trends appeared; lead-free soldering and the progressive miniaturization of electronic devices.
Technical Library | 2008-03-18 12:36:31.0
This paper examines the construction of a notebook mainboard with more than 2000 components and no wave soldering required. The board contains standard SMD, chipset BGAs, connectors, through hole components and odd forms placed using full automation and soldered after two reflow cycles under critical process parameters. However, state of the art technology does not help if the process parameters are not set carefully. Can all complex BGAs, THTs and even screws be soldered on a single stencil? What will help us overcome bridging, insufficient solder and thombstoning issues? This paper will demonstrate the placement of all odd shape components using pin-in-paste stencil design and full completion of the motherboard after two reflow cycles.
Technical Library | 2023-09-05 21:00:53.0
The head on pillow defect is becoming more common. This paper describes one such occurrence for an OEM and explains how it was dealt with. In this particular case it was solved by application of problem solving skills by the OEM, component supplier and the solder paste provider
Technical Library | 2019-07-24 23:55:32.0
Voiding is a key concern for components with thermal planes because interruptions in Z-axis continuity of the solder joint will hinder thermal transfer. When assembling components with solder paste, there is a high propensity for voiding due to the confined nature of the solder paste deposits under the component. Once reflowed, many factors contribute to the amount of voiding in a solder joint such as the reflow profile, designs of the component, board and stencil, and material factors. This study will focus on the solder paste alloy and flux combination as well as profile and board surface finishes.
Technical Library | 2008-10-29 18:45:53.0
Growing demand for compact, multi-function electronics products has accelerated component miniaturization and high-density placement, creating new challenges for the electronics manufacturing industry. It is no longer adequate to simply place parts accurately per a pre-defined CAD assembly program because solder paste alignment errors are increasing for numerous reasons. The solution to this problem is a system in which the placement machine can automatically detect and compensate for misalignment of the solder paste to produce high-quality boards regardless of the process errors beforehand.
Technical Library | 2021-12-08 01:19:32.0
In modern society, mobile phone is almost a necessity for everyone. When your mobile phone is not around, you may easily feel anxious as if something is missing, which is called nomophobia. In the past, people used to check if they had taken money when they went out. But now, mobile phone is the thing people must take. As is known to us, as long as you take a mobile phone, it's easy to get food, clothes, and to take transport. Look at our mobile phones, you will find almost all of them are equipped with touch screens now, which are much better than the early keyboard for using. So, how much do you know about HMI touch screens in industrial scenes?
Technical Library | 2007-06-06 15:25:30.0
Though today's microvias and high aspect plated through holes (PTH's) look nothing like the earliest through holes of 40 years ago, the PTH in its various forms remains the “weak link” and most critical element of printed wiring boards and laminate chip carriers (...) The paper outlines an approach to evaluating PTH reliability and quality that involves characterizing PTH life across a range of temperatures to reveal intricacies not seen by testing at a single delta-T, and certainly difficult to predict by modeling alone.
Technical Library | 2016-11-30 15:53:15.0
The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology, the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated, the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that it is sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes, blind, or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly.
Technical Library | 2018-04-18 23:55:01.0
Higher functionality, higher performance and higher reliability with smaller real estate are the mantras of any electronic device and the future guarantees more of the same. In order to achieve the requirements of these devices, designs must incorporate fine line and via pitch while maintain good circuitry adhesion at a smooth plating-resin interface to improve signal integrity. The Semi-Additive Process (SAP) is a production-proven method used on low dielectric loss tangent (Df) build-up materials that enables the manufacture of ultra-fine circuitry. (...) This paper will discuss a new SAP process for low loss build-up materials with low desmear roughness (Ra= 40-100 nm) and excellent adhesion (610-680 gf/cm) at various processing conditions. Along with the process flow, the current work will also present results and a discussion regarding characterization on the morphology and composition of resin and/or metal plating surfaces using scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX), surface roughness analysis, plating-resin adhesion evaluation from 90o peel tests
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
