Technical Library | 2015-03-04 10:56:26.0
As the proliferation of modern day electronics continues to drive miniaturization and functionality, electronic designers/assemblers face the issue of environmental exposure and uncommon applications never previously contemplated. This reality, coupled with the goal of reducing the environmental and health implications of the production and disposal of these devices, has forced manufacturers to reconsider the materials used in production. Furthermore, the need to increase package density and reduce costs has led to the rapid deployment of leadless packages such as QFN, POP, LGA, and Micro-BGA. In many cases, the manufacturers of these devices will recommend the use of no clean fluxes due to concerns over the ability to consistently remove flux residues from under and around these devices. These concerns, along with the need to implement a tin whisker mitigation strategy and/or increase environmental tolerance, have led to the conundrum of applying conformal coating over no clean residues.
Technical Library | 2016-10-03 08:28:47.0
With the miniaturization of electronic device, Land Grid Array (LGA) or QFN has been widely used in consumer electronic products. However there is only 20-30 microns gap left between LGA and the substrate, it is very difficult for capillary underfill to flow into the large LGA component at room temperature. Insufficient underfilling will lead to the loss of quality control and the poor reliability issue. In order to resolve these issues, a room temperature fast flow reworkable underfill has been successfully developed with excellent flowability. The underfill can flow into 20 microns gap and complete the flow of 15mm distance for about 30 seconds at room temperature. The curing behavior, storage, thermal cycling performance and reworkability will be discussed in details in this paper.
Technical Library | 2017-04-13 16:14:27.0
The drive to reduced size and increased functionality is a constant in the world of electronic devices. In order to achieve these goals, the industry has responded with ever-smaller devices and the equipment capable of handling these devices. The evolution of BGA packages and leadless devices is pushing existing technologies to the limit of current assembly techniques and materials.As smaller components make their way into the mainstream PCB assembly market, PCB assemblers are reaching the limits of Type 3 solder paste, which is currently in use by most manufacturers.The goal of this study is to determine the impact on solder volume deposition between Type 3, Type 4 and Type 5 SAC305 alloy powder in combination with stainless steel laser cut, electroformed and the emerging laser cut nano-coated stencils. Leadless QFN and μBGA components will be the focus of the test utilizing optimized aperture designs.
Technical Library | 2014-08-28 17:09:23.0
The fastest growing package types in the electronics industry today are Bottom Termination Components (BTCs). While the advantages of BTCs are well documented, they pose significant reliability challenges to users. One of the most common drivers for reliability failures is the inappropriate adoption of new technologies. This is especially true for new component packaging like BTCs. Obtaining relevant information can be difficult since information is often segmented and the focus is on design opportunities not on reliability risks (...)Commonly used conformal coating and potting processes have resulted in shortened fatigue life under thermal cycling conditions. Why do conformal coating and potting reduce fatigue life? This paper details work undertaken to understand the mechanisms underlying this reduction. Verification and determination of mechanical properties of some common materials are performed and highlighted. Recommendations for material selection and housing design are also given.
Technical Library | 2017-08-31 13:43:48.0
Wire bonded packages using conventional copper leadframe have been used in industry for quite some time. The growth of portable and wireless products is driving the miniaturization of packages resulting in the development of many types of thin form factor packages and cost effective assembly processes. Proper optimization of wire bond parameters and machine settings are essential for good yields. Wire bond process can generate a variety of defects such as lifted bond, cracked metallization, poor intermetallic etc. NSOP – non-stick on pad is a defect in wire bonding which can affect front end assembly yields. In this condition, the imprint of the bond is left on the bond pad without the wire being attached. NSOP failures are costly as the entire device is rejected if there is one such failure on any bond pad. The paper presents some of the failure modes observed and the efforts to address NSOP reduction
Technical Library | 2023-11-20 17:36:58.0
With PCB complexity and density increasing and also wider use of 3D devices, tougher requirements are now imposed on device inspection both during original manufacture and at their subsequent processing onto printed circuit boards. More complicated and dense packages have more opportunities to exhibit defects both internal to the package as well as to the PCB. As components increase in complexity their cost increases, making counterfeiting them a potentially lucrative business for unscrupulous individuals and organizations.
Technical Library | 2015-02-27 16:46:30.0
During the last period of newly assembled electrical devices (pcbs), new component types like LGA and QFN were also qualified as well as smaller passive components with reliability requirements based on the automotive and industrial industry. In the narrow gaps under components, residues can accumulate more by the capillary forces. This is not that much a surface resistance than an interface issue. Also that the flux residues under such types of components creates interaction with the solder resists from the pcb, as well as the component body was not completely described in the standard SIR measurement. On the other hand also, electrical influence with higher voltage creates new terms and conditions, in particular the combination of power and logic in such devices. The standard SIR measurement cannot analyze those combinations.The paper will discuss the requirements for a measurement process, and will give results. The influences of the pcb and component quality will also be discussed. Furthermore it will describe requirements for nc solder paste to increase the chemical/thermical/electrical reliability for whole devices
Technical Library | 2013-01-24 19:16:35.0
The electronics industry has mainly adopted the higher melting point Sn3Ag0.5Cu solder alloys for lead-free reflow soldering applications. For applications where temperature sensitive components and boards are used this has created a need to develop low melting point lead-free alloy solder pastes. Tin-bismuth and tin-bismuth-silver containing alloys were used to address the temperature issue with development done on Sn58Bi, Sn57.6Bi0.4Ag, Sn57Bi1Ag lead-free solder alloy pastes. Investigations included paste printing studies, reflow and wetting analysis on different substrates and board surface finishes and head-in-pillow paste performance in addition to paste-in-hole reflow tests. Voiding was also investigated on tin-bismuth and tin-bismuth-silver versus Sn3Ag0.5Cu soldered QFN/MLF/BTC components. Mechanical bond strength testing was also done comparing Sn58Bi, Sn37Pb and Sn3Ag0.5Cu soldered components. The results of the work are reported.
Technical Library | 2015-07-14 13:19:10.0
Bottom terminated components (BTC) are leadless components where terminations are protectively plated on the underside of the package. They are all slightly different and have different names, such as QFN (quad flat no lead), DFN (dual flat no lead), LGA (land grid array) and MLF (micro lead-frame. BTC assembly has increased rapidly in recent years. This type of package is attractive due to its low cost and good performance like improved signal speeds and enhanced thermal performance. However, bottom terminated components do not have any leads to absorb the stress and strain on the solder joints. It relies on the correct amount of solder deposited during the assembly process for having a good solder joint quality and reliable reliability. Voiding is typically seen on the BTC solder joint, especially on the thermal pad of the component. Voiding creates a major concern on BTC component’s solder joint reliability. There is no current industry standard on the voiding criteria for bottom terminated component. The impact of voiding on solder joint reliability and the impact of voiding on the heat transfer characteristics at BTC component are not well understood. This paper will present some data to address these concerns.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
