Technical Library | 2013-07-25 14:02:15.0
Bottom-termination components (BTC), such as QFNs, are becoming more common in PCB assemblies. These components are characterized by hidden solder joints. How are defects on hidden DFN joints detected? Certainly, insufficient solder joints on BTCs cannot be detected by manual visual inspection. Nor can this type of defect be detected by automated optical inspection; the joint is hidden by the component body. Defects such as insufficients are often referred to as "marginal" defects because there is likely enough solder present to make contact between the termination on the bottom-side of the component and the board pad for the component to pass in-circuit and functional test. Should the board be subjected to shock or vibration, however, there is a good chance this solder connection will fracture, leading to an open connection.
Technical Library | 2018-03-07 22:41:05.0
This study investigates the scooping effect during solder paste printing as a function of aperture width, aperture length and squeegee pressure. The percent of the theoretical volume deposited depends on the PWB topography. A typical bimodal percent volume distribution is attributed to poor release apertures and large apertures, where scooping takes place, yielding percent volumes 100%. This printing experiment is done with a concomitant validation of the printing process using standard 3D Solder Paste Inspection (SPI) equipment.
Technical Library | 2012-08-30 21:24:29.0
This paper provides definitions of the different voiding types encountered in Gull Wing solder joint geometries. It further provides corresponding reliability data that support some level of inclusion voiding in these solder joints and identifies the final criteria being applied for certain IBM Server applications. Such acceptance criteria can be applied using various available x-ray inspection techniques on a production or sample basis. The bulk of supporting data to date has been gathered through RoHS server exempt SnPb eutectic soldering operations but it is expected to provide a reasonable baseline for pending Pb-free solder applications.
Technical Library | 2015-10-01 16:12:51.0
Solder paste printing is known to be one of the most difficult processes to quality assure in electronic manufacturing. The challenge increases as the technology development moves toward a mix between large modules and small chip components on large and densely populated printed circuit boards. Having a process for quality assurance of the solder paste print is fast becoming a necessity.This article describes a method to ensure quality secured data from both solder paste printers and inspection machines in electronic assembly manufacturing. This information should be used as feedback in order to improve the solder paste printing process.
Technical Library | 2022-02-21 19:49:16.0
The ability to undertake non-destructive testing on semiconductor devices, during both their manufacture and their subsequent use in printed circuit boards (PCBs), has become ever more important for checking product quality without compromising productivity. The use of x-ray inspection not only provides a potentially non-destructive test but also allows investigation within optically hidden areas, such as the wire bonding within packages and the quality of post solder reflow of area array devices (e.g. BGAs, CSPs and flip chips).
Technical Library | 2023-01-17 17:16:43.0
A test program was developed to evaluate the effectiveness of vacuum reflow processing on solder joint voiding and subsequent thermal cycling performance. Area array package test vehicles were assembled using conventional reflow processing and a solder paste that generated substantial void content in the solder joints. Half of the population of test vehicles then were re-processed (reflowed) using vacuum reflow. Transmission x-ray inspection showed a significant reduction in solder voiding after vacuum processing. The solder attachment reliability of the conventional and vacuum reflowed test vehicles was characterized and compared using two different accelerated thermal cycling profiles. The thermal cycling results are discussed in terms of the general impact of voiding on solder thermal fatigue reliability, results from the open literature, and the evolving industry standards for solder voiding. Recommendations are made for further work based on other void reduction methods and additional reliability studies.
Technical Library | 2023-08-04 15:38:36.0
The MicroLeadFrame® (MLF®)/Quad Flat No-Lead (QFN) packaging solution is extremely popular in the semiconductor industry. It is used in applications ranging from consumer electronics and communications to those requiring high reliability performance, such as the automotive industry. The wide acceptance of this packaging design is primarily due to its flexible form factors, size, scalability and thermal dissipation capabilities. The adaptation and acceptance of MLF/QFN packages in automotive high reliability applications has led to the development of materials and processes that have extended its capabilities to meet the performance and quality requirements. One of process developments that is enabling the success of the MLF/QFN within the automotive industry has been the innovation of side wettable flanks that provide the capability to inspect the package lead to printed circuit board (PCB) interfaces for reliable solder joints. Traditionally, through-board X-ray was the accepted method for detecting reliable solder joints for leadless packages. However, as PBC layer counts and routing complexities have increased, this method to detect well-formed solder fillets has proven ineffective and incapable of meeting the inspection requirements. To support increased reliability and more accurate inspection of the leadless package solder joints, processes to form side-wettable flanks have been developed. These processes enable the formation of solder fillets that are detectable using state-of-the-art automated optical inspection (AOI) equipment, providing increased throughput for the surface mount technology (SMT) processes and improved quality as well.
Technical Library | 2021-08-04 18:46:25.0
The process of printed circuit board assembly (PCBA) involves several machines, such as a stencil printer, placement machine and reflow oven, to solder and assemble electronic components onto printed circuit boards (PCBs). In the production flow, some failure prevention mechanisms are deployed to ensure the designated quality of PCBA, including solder paste inspection (SPI), automated optical inspection (AOI) and in-circuit testing (ICT). However, such methods to locate the failures are reactive in nature, which may create waste and require additional effort to be spent re-manufacturing and inspecting the PCBs. Worse still, the process performance of the assembly process cannot be guaranteed at a high level. Therefore, there is a need to improve the performance of the PCBA process. To address the aforementioned challenges in the PCBA process, an intelligent assembly process improvement system (IAPIS) is proposed, which integrates the k-means clustering method and multi-response Taguchi method to formulate a pro-active approach to investigate and manage the process performance.
Technical Library | 2001-05-03 11:23:09.0
In this age of global competition, world class electronics manufacturers understand that increasing profit margins is accomplished not by increasing price or lowering the quality of components and workmanship, but by increasing production yields. Post-solder inspection ensures that your customers receive good product, but by separating the good boards from the bad boards you only measure yield, not improve it. A yield (and profit) improvement strategy consists of making measurements at critical stages, as early as possible in the assembly process, and adjusting the process parameters to achieve optimal performance.
Technical Library | 2007-03-28 10:18:33.0
Legislation against the use of lead in electronics has been the driving force behind the use of lead-free solders, surface finishes, and component lead finishes. The major concern in using lead-free solders in the assembly and rework Chip Scale Packages (CSPs) is the relatively high temperatures that the components and the boards experience. Fine-pitch CSPs have very low standoff heights following assembly making inspection and rework of these components more difficult. One other concern pertinent to rework is the temperature of the neighboring components during rework. These issues, coupled with the limitations of rework equipment to handle lead-free reflow temperatures, make the task of reworking lead-free assemblies more challenging.
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