Technical Library | 2019-12-26 19:13:52.0
Plated through hole (PTH) plays a critical role in printed circuit board (PCB) reliability. Thermal fatigue deformation of the PTH material is regarded as the primary factor affecting the lifetime of electrical devices. Numerous research efforts have focused on the failure mechanism model of PTH. However, most of the existing models were based on the one-dimensional structure hypothesis without taking the multilayered structure and external pad into consideration.In this paper, the constitutive relation of multilayered PTH is developed to establish the stress equation, and finite element analysis (FEA) is performed to locate the maximum stress and simulate the influence of the material properties. Finally, thermal cycle tests are conducted to verify the accuracy of the life prediction results. This model could be used in fatigue failure portable diagnosis and for life prediction of multilayered PCB.
Technical Library | 2019-08-07 22:56:45.0
The requirement to reconsider traditional soldering methods is becoming more relevant as the demand for bottom terminated components (QFN/BTC) increases. Thermal pads under said components are designed to enhance the thermal and electrical performance of the component and ultimately allow the component to run more efficiently. Additionally, low voiding is important in decreasing the current path of the circuit to maximize high speed and RF performances. The demand to develop smaller, more reliable, packages has seen voiding requirements decrease below 15 percent and in some instances, below 10 percent.Earlier work has demonstrated the use of micro-fluxed solder preforms as a mechanism to reduce voiding. The current work builds upon these results to focus on developing an engineered approach to void reduction in leadless components (QFN) through increasing understanding of how processing parameters and a use of custom designed micro-fluxed preforms interact. Leveraging the use of a micro-fluxed solder preform in conjunction with low voiding solder paste, stencil design, and application knowhow are critical factors in determining voiding in QFN packages. The study presented seeks to understand the vectors that can contribute to voiding such as PCB pad finish, reflow profile, reflow atmosphere, via configuration, and ultimately solder design.A collaboration between three companies consisting of solder materials supplier, a power semiconductor supplier, and an electronic assembly manufacturer worked together for an in-depth study into the effectiveness of solder preforms at reducing voiding under some of the most prevalent bottom terminated components packages. The effects of factors such as thermal pad size, finish on PCB, preform types, stencil design, reflow profile and atmosphere, have been evaluated using lead-free SAC305 low voiding solder paste and micro-fluxed preforms. Design and manufacturing rules developed from this work will be discussed.
Technical Library | 2022-10-11 20:15:14.0
The increased temperatures associated with Pb-free processes have produced significant challenges for PWB laminates. Newly developed laminates have different curing processes, are commonly filled with ceramic particles or micro-clays and can have higher Tg values. These changes which are aimed at improving the materials resistance to thermal excursions and maintaining electrical integrity through primary attach and rework operations have also had the effect of producing harder resin systems with lower fracture toughness.
Technical Library | 2019-09-24 15:41:53.0
This paper focuses on three different coating material groups which were formulated to operate under high thermal stress and are applied at printed circuit board manufacturing level. While used for principally different applications, these coatings have in common that they can be key to a successful thermal management concept especially in e-mobility and lighting applications. The coatings consist of: Specialty (green transparent) liquid photoimageable solder masks (LPiSM) compatible with long-term thermal storage/stress in excess of 150°C. Combined with the appropriate high-temperature base material, and along with a suitable copper pre-treatment, these solder resists are capable of fulfilling higher thermal demands. In this context, long-term storage tests as well as temperature cycling tests were conducted. Moreover, the effect of various Cu pre-treatment methods on the adhesion of the solder masks was examined following 150, 175 and 200°C ageing processes. For this purpose, test panels were conditioned for 2000 hours at the respective temperatures and were submitted to a cross-cut test every 500 h. Within this test set-up, it was found that a multi-level chemical pre-treatment gives significantly better adhesion results, in particular at 175°C and 200°C, compared with a pre-treatment by brush or pumice brush. Also, breakdown voltage as well as tracking resistance were investigated. For an application in LED technology, the light reflectivity and white colour stability of the printed circuit board are of major importance, especially when high-power LEDs are used which can generate larger amounts of heat. For this reason, a very high coverage power and an intense white colour with high reflectivity values are essential for white solder masks. These "ultra-white" and largely non-yellowing LPiSM need to be able to withstand specific thermal loads, especially in combination with high-power LED lighting applications. The topic of thermal performance of coatings for electronics will also be discussed in view of printed heatsink paste (HSP) and thermal interface paste (TIP) coatings which are used for a growing number of applications. They are processed at the printed circuit board manufacturing level for thermal-coupling and heat-spreading purposes in various thermal management-sensitive fields, especially in the automotive and LED lighting industries. Besides giving an overview of the principle functionality, it will be discussed what makes these ceramic-filled epoxy- or silicone-based materials special compared to using "thermal greases" and "thermal pads" for heat dissipation purposes.
Technical Library | 2021-08-25 16:28:36.0
In this study, a Sn–Bi composite solder paste with thermosetting epoxy (TSEP Sn–Bi) was prepared by mixing Sn–Bi solder powder, flux, and epoxy system. The melting characteristics of the Sn–Bi solder alloy and the curing reaction of the epoxy system were measured by differential scanning calorimeter (DSC). A reflow profile was optimized based on the Sn–Bi reflow profile, and the Organic Solderability Preservative (OSP) Cu pad mounted 0603 chip resistor was chosen to reflow soldering and to prepare samples of the corresponding joint. The high temperature and humidity reliability of the solder joints at 85 #14;C/85% RH (Relative Humidity) for 1000 h and the thermal cycle reliability of the solder joints from
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
Technical Library | 2016-02-11 18:26:43.0
Although reflow ovens may not have been dramatically changed during the last decade the reflow process changes step by step. With the introduction of lead-free soldering not only operation temperatures increased, but also the chemistry of the solder paste was modified to meet the higher thermal requirements. Miniaturization is a second factor that impacts the reflow process. The density on the assembly is increasing where solder paste deposit volumes decreases due to smaller pad and component dimensions. Pick and place machines can handle more components and to meet this high through put some SMD lines are equipped with dual lane conveyors, doubling solder paste consumption. With the introduction of pin in paste to solder through hole components contamination of the oven increased due to dripping of the paste.
Technical Library | 2021-05-26 00:53:26.0
This paper describes a copper electroplating enabling technology for filling microvias. Driven by the need for faster, smaller and higher performance communication and electronic devices, build-up technology incorporating microvias has emerged as a viable multilayer printed circuit manufacturing technology. Increased wiring density, reduced line widths, smaller through-holes and microvias are all attributes of these High Density Interconnect (HDI) packages. Filling the microvias with conductive material allows the use of stacked vias and via in pad designs thereby facilitating additional packaging density. Other potential design attributes include thermal management enhancement and benefits for high frequency circuitry. Electrodeposited copper can be utilized for filling microvias and provides potential advantages over alternative via plugging techniques. The features, development, scale up and results of direct current (DC) and periodic pulse reverse (PPR) acid copper via filling processes, including chemistry and equipment, are described.
Technical Library | 2015-07-14 13:19:10.0
Bottom terminated components (BTC) are leadless components where terminations are protectively plated on the underside of the package. They are all slightly different and have different names, such as QFN (quad flat no lead), DFN (dual flat no lead), LGA (land grid array) and MLF (micro lead-frame. BTC assembly has increased rapidly in recent years. This type of package is attractive due to its low cost and good performance like improved signal speeds and enhanced thermal performance. However, bottom terminated components do not have any leads to absorb the stress and strain on the solder joints. It relies on the correct amount of solder deposited during the assembly process for having a good solder joint quality and reliable reliability. Voiding is typically seen on the BTC solder joint, especially on the thermal pad of the component. Voiding creates a major concern on BTC component’s solder joint reliability. There is no current industry standard on the voiding criteria for bottom terminated component. The impact of voiding on solder joint reliability and the impact of voiding on the heat transfer characteristics at BTC component are not well understood. This paper will present some data to address these concerns.
Technical Library | 2016-11-17 14:37:41.0
With increasing LED development and production, thermal issues are becoming more and more important for LED devices, particularly true for high power LED and also for other high power devices. In order to dissipate the heat from the device efficiently, Au80Sn20 alloy is being used in the industry now. However there are a few drawbacks for Au80Sn20 process: (1) higher soldering temperature, usually higher than 320°C; (2) low process yield; (3) too expensive. In order to overcome the shortcomings of Au80Sn20 process, YINCAE Advanced Materials, LLC has invented a new solderable adhesive – TM 230. Solderable adhesives are epoxy based silver adhesives. During the die attach reflow process, the solder material on silver can solder silver together, and die with pad together. After soldering, epoxy can encapsulate the soldered interface, so that the thermal conductivity can be as high as 58 W/mk. In comparison to Au80Sn20 reflow process, the solderable adhesive has the following advantages: (1) low process temperature – reflow peak temperature of 230°C; (2) high process yield – mass reflow process instead of thermal compression bonding process; (3) low cost ownership. In this paper we are going to present the die attach process of solderable adhesive and the reliability test. After 1000 h lighting of LED, it has been found that there is almost no decay in the light intensity by using solderable adhesive – TM 230.
