Technical Library | 2023-04-17 17:05:47.0
In an ideal world, manufacturing devices would work all of the time, however, every company receives customer returns for a variety of reasons. If these returned parts contributed to a fail, most companies will perform failure analysis (FA) on the returned parts to determine the root cause of the failure. Failure can occur for a multitude of reasons, for example: wear out, fatigue, design issues, manufacturing flaw or defect. This information is then used to improve the overall quality of the product and prevent reoccurrence. If no defect is found, it is possible that in fact the product has no defect. On the other hand, the defect could be elusive and the FA techniques insufficient to detect said deficiency. No-clean flux residues can cause intermittent or elusive, hard to find defects. In an attempt to understand the effects of no-clean flux residues from the secondary soldering and cleaning processes, a matrix of varying process and cleaning operation was investigated. Of special interest, traveling flux residues and entrapped residues were examined, as well as localized and batch cleaning processes. Various techniques were employed to test the remaining residues in order to assess their propensity to cause a latent failure. These techniques include Surface Insulation Resistance1 (SIR) testing at 40⁰C/90% RH, 5 VDC bias along with C32 testing and Ion Exchange Chromatography (IC). These techniques facilitate the assessment of the capillary effect the tight spacing these component structures have when flux residues are present. It is expected that dendritic shorting and measurable current leakage will occur, indicating a failing SIR test. However, since the residue resides under the discrete components, there will be no visual evidence of dendritic growth or metal migration.
Technical Library | 2023-06-02 17:37:43.0
This presentation of Nano Dimension Ltd. (the"Company") contains "forward-looking statements" within the meaning of the Private Securities Litigation Reform Act and other securities laws. Words such as "expects," "anticipates, " "intends, " "plans, " "believes, " "seeks, " "estimates" and similar expressions or variations of such words are intended to identify forward-looking statements. For example, the Company is using forward-looking statements when it discuss the potential of its products, strategic growth plan, its business plan and investment plans, the size fits addressable market, market growth, and expected recurring revenue growth. Forward-looking statements are no historical facts, and are based upon management's current expectations, beliefs and projections, many of which, by their nature, are inherently uncertain. Such expectations, beliefs and projections are expressed in good faith. However, there can be assurance that management's expectations, beliefs and projections will be achieved, and actual results may differ materially from what is expressed in or indicated by the forward-looking statements. Forward-looking statements are subject to risks and uncertainties that could cause actual performance or results to differ materially from those expressed in the forward-looking statements. For a more detailed description of the risks and uncertainties affecting the Company, reference is made to the Company's reports filed from time to time with the Securities and Exchange Commission ("SEC"), including, but not limited to, the risks detailed in the Company's annual report for the year ended December 31st, 2020, filed with the SEC. Forward-looking statements speak only as of the date the statements are made. The Company assumes no obligation to update forward-looking statements to reflect actual results, subsequent events or circumstances, changes in assumptions or changes in other factors affecting forward-looking information except to the extent required by applicable securities laws. If the Company does update one or more forward-looking statements, no inference should be drawn that the Company will make additional updates with respect thereto or with respect to other forward-looking statements.
Technical Library | 2021-07-20 20:02:29.0
During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability.
