Electronics Forum | Wed Jun 04 18:46:10 EDT 2014 | hegemon
Well, we cannot make the cuts any deeper as then > we would incur a significant amount of "bowing" > at SMT placement/reflow. Interesting. Could be a number of factors contributing. Here's a story.... In the beginning was the board design, and in
Electronics Forum | Wed Aug 20 14:16:57 EDT 2014 | jax
I have a few questions: Why are you unable to panelize an aluminum board? We run aluminum boards all the time utilizing both V-Score and Routed designs. Panelization aside, what are the issues that you run into at printing? Are you trying to print
Electronics Forum | Thu Oct 04 15:50:32 EDT 2007 | naynayno
Being that is budgeting season I am interested in specifying more depaneling equipment but with an eye towards quality / realiability. We use routing for COB assemblies but have spec'd the Cab 4M for everything else. However, I came across a Frost
Electronics Forum | Fri Apr 08 17:23:34 EDT 2005 | KEN
Warpage factors can cause: 1. Boards can not transfer down conveyor belts or wedge at transitions. 2. May not enter into machinery due to interferences (like board clamps) 3. May fall off conveyor chain in furnace. Especially true of thin (PCMCI
Electronics Forum | Tue Nov 28 11:58:58 EST 2017 | emeto
Hello all, I am about to design a panel and there are two connectors on the board that seem to be very close to the edge of the board. I am worried that they might interfere with the cutter blade. Can you tell me how close do you think a part should
Electronics Forum | Wed May 22 10:14:08 EDT 2019 | emeto
Matt, we did the study and YES perpendicular to the V-score is the worst case scenario. We did a cross section and confirmed component is cracked. If you don't have power over PCB design, the easiest way is to change board panelization or even order
Electronics Forum | Sat Jul 23 02:16:52 EDT 2022 | poly
Is there are reason for going for larger (or smaller) boards when designing panels for use with a chain conveyor oven? My panels range from 0.6mm 2 layer (for touch with hatched ground) to 1.6mm 4 layer. I'm planning to go for smaller panels to reduc
Electronics Forum | Fri Mar 03 16:05:42 EST 2006 | Chris
Hi, Anyone ever perform a DOE on prepreg glass bundle direction or glass bundle grain and how or if it affects PCB warpage and chip component cracking at V-score depanel? Since most FR4 and prepreg has has 1.4 times more fiber bundles in one direct
Electronics Forum | Wed Mar 21 10:30:15 EDT 2007 | ck_the_flip
Chrissie also says, "Before anyone suggests it - redesign of the boards is not an option!!", so I'm assuming that re-design means panelization too. She's probably sitting on thousands of these unpanelized PCB's in stock. Now, for the future, as Ste
Electronics Forum | Wed Aug 01 11:03:20 EDT 2001 | Chip Gill
I read your request for design information on panel layout for V-scoring, and felt the need to respond. Scored PWB's are indeed more efficient to produce and depanel than tab routed PWB's, but there are also drawbacks associated with this method. T
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