Electronics Forum | Wed Jul 14 15:36:34 EDT 2010 | remullis
98% to 99% pass yield should be your target. The previous company I worked for, we were able to meet these goals with most all of our products. It took us some years to achieve this level of pass rate. Of course analyzing and good reporting from some
Electronics Forum | Mon Feb 25 15:09:06 EST 2002 | jax
Kelvin, You can find the Standard acceptable levels and testing procedures from IPC. Here's a little advice from the fellas' over at PCFAB: As a guideline, we recommend that for assemblies processed with low-solids flux technology and that are not cl
Electronics Forum | Mon Feb 25 21:13:12 EST 2002 | davef
No, none of us can tell you what is the acceptable level of halide content or contamination in flux residue. The level of harmful residues on your product helps determine the reliability of your product. We know nothing of your product, its custome
Electronics Forum | Sat Jan 15 16:59:47 EST 2000 | Steve Thomas
Thanks, Mark. Actually we already have an established mark. We use 500ppm (99.95%) as our acceptable level. Problem is, someone (another manufacturer) told someone else (our pres.) that THEY build to 50ppm. Soooooo, someone else told my boss that
Electronics Forum | Mon Jan 17 12:16:02 EST 2000 | Brian W.
My old company (CM) ran SMT to 50ppm including some very complex boards. We established the normalizer number by: #components + #solder joints. As was stated earlier, the ppm for any given product is the result of many factors. You may get differen
Electronics Forum | Mon Feb 25 14:32:37 EST 2002 | Kelvin
We always talk about the halide free fluxes and solder pastes. Is there anyone tell me what is the industrial acceptable level of halide content or contamination in flux residue? All comment are welcome !!! Kelvin
Electronics Forum | Wed Sep 15 06:53:48 EDT 2004 | John
Hi Everybody, Can enybody tell me what is acceptable level of defects for Wave soldering?I know that it's depends of many factors,but I want to benchmark my process. Thank you
Electronics Forum | Sun Dec 17 22:55:45 EST 2006 | foolat
I'd like to know how much capacitor offset from the pad should be acceptable? What are the risks of the placement offset if greater than the acceptable level? I'm still quite new to this so any help will be very much appreciated. Thanks
Electronics Forum | Wed May 23 10:11:43 EDT 2012 | blnorman
Simple answer is no, there is no universally acknowledged acceptance criteria. Some time ago, I started a spreadsheet with the acceptance levels suggested by various labs on the individual ionic species. All are relatively close in their individual
Electronics Forum | Wed Sep 15 09:49:28 EDT 2004 | pjc
zero- strive for no post wave "touch-up"
