Technical Library | 2021-05-06 13:48:05.0
In this paper most commonly occurring Bare PCB defects such as Track Cut, Track short and Pad Damages are detected by Image processing techniques. Reference PCB without having any defects is compared with test PCB having defects to identify the defects and x-y coordinates of the center of the defects along with radii are obtained using Difference of Gaussian method and location of the individual type of defects are marked either by similar color or different colors. Result Analysis includes time taken for the inspection of a single defect, multiple similar defects, and multiple different defects. Time taken is ranging from 1.674 to 1.714 seconds if the individual type of defects are marked by different colors and 0.670 to 0.709 seconds if all the identified defects are marked by the same colors.
Technical Library | 2016-04-21 14:10:55.0
The world of electronics continues to increase functional densities on products. One of the ways to increase density of a product is to utilize more of the 3 dimensional spaces available. Traditional printed circuit boards utilize the x/y plane and many miniaturization techniques apply to the x/y space savings, such as smaller components, finer pitches, and closer component to component distances.This paper will explore the evolution of 3D assembly techniques, starting from flexible circuit technology, cavity assembly, embedded technology, 3 dimensional surface mount assembly, etc.
Technical Library | 2013-01-17 15:34:33.0
The use of an electroless nickel, immersion gold (ENIG) surface finish comes with the inherent potential risk of Black Pad failures that can cause fracture embrittlement at the interface between the solder and the metal pad. As yet, there is no conclusive agreed solution to effectively eliminate Black Pad failures. The case studies presented are intended to add to the understanding of the Black Pad failure mechanism and to identify both the plating and the subsequent assembly processes and conditions that can help to prevent the likelihood of Black Pad occurring.
Technical Library | 2023-05-02 19:06:43.0
As 0402 has become a common package for printed circuit board (PCB) assembly, research and development on mounting 0201 components is emerging as an important topic in the field of surface mount technology for PWB miniaturization. In this study, a test vehicle for 0201 packages was designed to investigate board design and assembly issues. Design of Experiment (DOE) was utilized, using the test vehicle, to explore the influence of key parameters in pad design, printing, pick-andplace, and reflow on the assembly process. These key parameters include printing parameters, mounting height or placement pressure, reflow ramping rate, soak time and peak temperature. The pad designs consist of rectangular pad shape, round pad shape and home-based pad shape. For each pad design, several different aperture openings on the stencil were included. The performance parameters from this experiment include solder paste height, solder paste volume and the number of post-reflow defects. By analyzing the DOE results, optimized pad designs and assembly process parameters were determined.
Technical Library | 2015-06-11 21:20:29.0
The use of bottom terminated components (BTC) has become widespread, specifically the use of Quad Flat No-lead (QFN) packages. The small outline and low height of this package type, improved electrical and thermal performance relative to older packaging technology, and low cost make the QFN/BTC attractive for many applications.Over the past 15 years, the implementation of the QFN/BTC package has garnered a great amount of attention due to the assembly and inspection process challenges associated with the package. The difference in solder application parameters between the center pad and the perimeter pads complicates stencil design, and must be given special attention to balance the dissimilar requirements
Technical Library | 2008-09-04 17:57:24.0
In the quest for lower ESL devices, having the ESL reduced in the package is only half of the battle; connecting that device to the circuit determines how much of that low ESL appears to the circuit. For this low ESL part type, it would be a shame to take a part of 200 pH and add 2000 pH to its ESL because of via patterns on the PCB.
Technical Library | 2012-10-18 21:58:51.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. In this paper, we report on a comprehensive study regarding the morphology evolution and voiding of SnAgCu solder joints on the central pad of two different packages – QFN and an Agilent package called TOPS – on PCBs with a Ni/Au surface finish.
Technical Library | 2022-07-11 09:24:48.0
The change of squeegee pressure has a significant impact on printing. Too small pressure will make the solder paste unable to effectively reach the bottom of the stencil opening and not be well deposited on the pad. Too much pressure will cause tin The paste is printed too thin and can even damage the stencil.
Technical Library | 2019-04-17 21:29:14.0
Electroless nickel electroless palladium immersion gold (ENEPIG) surface finish for printed circuit board (PCB) has now become a key surface finish that is used for both tin-lead and lead-free solder assemblies. This paper presents the reliability of land grid array (LGA) component packages with 1156 pads assembled with tin-lead solder onto PCBs with an ENEPIG finish and then subjected to thermal cycling and then isothermal aging.
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
