Electronics Forum | Thu Nov 09 20:11:58 EST 2006 | darby
Very much agree with Russ, Are your CM's doing final test and assembly? If so I would think that 95% is in the ballpark. If not, very much product dependant.
Electronics Forum | Thu Jul 28 22:35:58 EDT 2011 | davef
The consequences of poor heel formation in solder connections include: * Lower solder joint strength * Possible intermittent short circuits * Reduced first-pass yields * Increased inspection cost * Increased rework cost * Likely field failures * Like
Electronics Forum | Thu Jul 10 08:18:15 EDT 2014 | emeto
I think what you are asking for is called First Pass Yield and for us that is in the upper 90s. It will depend on the board complexity and quantity - makes big difference if you run 10pcs or a 10000pcs. Regards, Emil
Electronics Forum | Thu Apr 30 23:28:17 EDT 2020 | SMTA-Davandran
Do considering AR and 5 balls rule during designing stencil aperture. it give better paste release. Aperture redesigning need to look into symptom that we are seeing on AOI. It will be given us idea hows to improve aperture design to improve SMT firs
Electronics Forum | Fri Nov 17 14:55:27 EST 2006 | CK the Flip
Typical of QE types. They don't know the entire process of qualifying what makes a "good" board (besides FPY), so they just arbitrarily come up with 95% FPY as a benchmark. Russ made a great point that alot of yield issues are design-related. Typi
Electronics Forum | Thu Mar 29 08:58:06 EDT 2007 | chrissieneale
Started measuring rework last week - on some of the boards we are looking at a shocking 20% right first time yield. The paste thing has to be fixed as it's being left more than four hours. Thanks for all the comments - Will let everyone know the re
Electronics Forum | Thu Jul 18 12:33:21 EDT 2002 | slthomas
Not sure if you're trying to improve your defect rate (we use dpmo) or your test yield. The question is what do you do if you're happy with your dpmo levels but not some of your first pass yield numbers because certain boards have more parts. Inspe
Electronics Forum | Wed Jun 11 09:58:35 EDT 2003 | swagner
Solder fillet inspection is something that I would avoid like SARS, solder joints are like a snowflake no two are the same, henceforth unrepeatability. The only time I would look into this would be for uBGA or flipchip on an audit basis utilizing X-
Electronics Forum | Sat Dec 27 01:32:42 EST 2003 | Ian Chan
IMHO, depending on whether its a regular run model, or a properly designed/setup pilot run model, getting a mean 75%-95% First Pass Yield (FPY%) is possible as a benchmark target. This is derived from your manufacturing history capabilities, and requ
Electronics Forum | Fri Jul 06 18:21:24 EDT 2001 | davef
Maybe someone else can help, like: http://www.ceeris.com/efficiency.htm. Check with the following SMTnetters: * Steve Gregory. He posted a thread within the past week or so on solderability testing. He used to work at a memory module manufacturer
