Technical Library | 2022-10-31 18:35:40.0
Voids affect the thermal characteristics and mechanical properties of a solder joint, thereby affecting the reliability of the solder interconnect. The automotive sector in particular is requiring the mitigation of solder voids in various electronic control modules to the minimum possible level. Earlier research efforts performed to decrease voids involved varying the reflow profile, paste deposit, paste alloy composition, stencil aperture, and thickness. Due to the various advantages they offer, the use of Ball Grid Array packages is common across all industry sectors. They are also prone to process voiding issues. This study was performed to determine if vacuum assisted reflow process can help alleviate the voids in area array solder joints. Test parameters in this study largely focused on vacuum pressure level and vacuum dwell time.
Technical Library | 2008-03-18 12:36:31.0
This paper examines the construction of a notebook mainboard with more than 2000 components and no wave soldering required. The board contains standard SMD, chipset BGAs, connectors, through hole components and odd forms placed using full automation and soldered after two reflow cycles under critical process parameters. However, state of the art technology does not help if the process parameters are not set carefully. Can all complex BGAs, THTs and even screws be soldered on a single stencil? What will help us overcome bridging, insufficient solder and thombstoning issues? This paper will demonstrate the placement of all odd shape components using pin-in-paste stencil design and full completion of the motherboard after two reflow cycles.
Technical Library | 2020-12-29 20:55:46.0
Voiding in solder joints has been studied extensively, and the effects of many variables compared and contrasted with respect to voiding performance. Solder paste flux, solder powder size, stencil design, circuit board design, via-in-pad design, surface finish, component size, reflow profile, vacuum reflow, nitrogen reflow and other parameters have been varied and voiding quantified for each. The results show some differences in voiding performance with respect to most of these variables but these variables are not independent of each other. Voiding in solder joints is a complex issue that often requires multiple approaches to reduce voiding below required limits. This paper focuses on solutions to voiding for commonly used bottom terminated components (BTCs).
Technical Library | 2016-01-12 11:03:35.0
With the pitch size of interconnect getting finer and finer, the bonding strength between flexible and rigid (e.g. PCB, ceramic) substrates becomes a serious issue because it is not strong enough to meet the customer’s requirement. Capillary underfill has been used to enhance the bonding strength between flexible and rigid substrates, but the enhancement is very limited, particularly for high temperature application. The bonding strength of underfilled flexible/rigid interconnect is dramatically decreased after being used at 180◦C, and the interconnects are weakened by the internal stress caused by the expansion of underfill at high temperatures. In order to resolve reliability issues of the interconnect between flexible/rigid substrates, solder joint encapsulant was implemented into the thermal compression bonding process, which was used to manufacture the interconnect between flexible/rigid substrates. Compared to the traditional process, the strength of the interconnect was doubled and the reliability was significantly improved in high temperature application.
Technical Library | 2020-05-07 03:46:27.0
The selective soldering process has evolved to become a standard production process within the electronics assembly industry, and now accommodates a wide variety of through-hole component formats in numerous applications. Most through-hole components can be easily soldered with the selective soldering process without difficulty, however some types of challenging components require additional attention to ensure optimum quality control is maintained. Several high thermal mass components can place demands on the selective soldering process, while the use of specialized solder fixtures and/or pallets often places an additional thermal demand on the preheating process. Fine-pitch through-hole components and connectors place a different set of demands on the selective soldering process and typically require special attention to lead projection and traverse speed to minimize bridging between adjacent pins. Dual in-line memory module (DIMM) connectors, compact peripheral component interface (cPCI) connectors, coax connectors and other high thermal mass components as well as fine-pitch microconnectors,can present challenges when soldered into backplanes or multilayer printed circuit board assemblies. Adding to this challenge, compact peripheral component interface connectors can present additional solderability issues due to their beryllium copper termination pins.
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
Technical Library | 2006-10-02 14:26:47.0
This paper addresses the assembly and reliability of 0.5 mm pitch leadless Chip Scale Packages (CSP) on .062" immersion Ag plated printed circuit boards (PCB) using Pb-free solder paste. Four different leadless CSP designs were studied and each was evaluated using multiple PCB attachment pad designs.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
Technical Library | 2019-03-06 21:26:14.0
Electronic assemblies use a large variety of polymer materials with different mechanical and thermal properties to provide protection in harsh usage environments. However, variability in the mechanical properties such as the coefficient of thermal expansion and elastic modulus effects the material selection process by introducing uncertainty to the long term impacts on the reliability of the electronics. Typically, the main reliability issue is solder joint fatigue which accounts for a large amount of failures in electronic components. Therefore, it is necessary to understand the effect of polymer encapsulations (coatings, pottings and underfills) on the solder joints when predicting reliability.This paper presents the construction and validation of a thermo-mechanical tensile fatigue specimen. The thermal cycling range was matched with potting expansion properties in order to vary the magnitude of tensile stress imposed on solder joints
Technical Library | 2013-01-24 19:16:35.0
The electronics industry has mainly adopted the higher melting point Sn3Ag0.5Cu solder alloys for lead-free reflow soldering applications. For applications where temperature sensitive components and boards are used this has created a need to develop low melting point lead-free alloy solder pastes. Tin-bismuth and tin-bismuth-silver containing alloys were used to address the temperature issue with development done on Sn58Bi, Sn57.6Bi0.4Ag, Sn57Bi1Ag lead-free solder alloy pastes. Investigations included paste printing studies, reflow and wetting analysis on different substrates and board surface finishes and head-in-pillow paste performance in addition to paste-in-hole reflow tests. Voiding was also investigated on tin-bismuth and tin-bismuth-silver versus Sn3Ag0.5Cu soldered QFN/MLF/BTC components. Mechanical bond strength testing was also done comparing Sn58Bi, Sn37Pb and Sn3Ag0.5Cu soldered components. The results of the work are reported.
