Industry News | 2013-03-28 11:03:15.0
Multitest, will present at the VOICE conference, scheduled to take place April 23-25, 2013 at the DoubleTree by Hilton Hotel in San Jose, CA. Meet Multitest’s experts to learn more about the company’s solutions, from wafer-level test to final test – for standard ICs and sensor packages.
Industry News | 2013-04-11 18:53:28.0
Multitest, will present at the Teradyne Users Group Conference, scheduled to take place April 29-May 1, 2013 in Fort Worth, TX. Meet Multitest’s experts to learn more about the company’s solutions, from wafer-level test to final test – for standard ICs and sensor packages.
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Industry News | 2019-11-05 22:08:21.0
Via in pad is the design practice of placing a via in the copper landing pad of a component. Compared to standard PCB via routing, via in pad allows a design to use smaller component pitch sizes and further reduce the PCBs overall size. With component manufactures pushing smaller parts every year and the demand from consumers for smaller devices, the usage of via in pad practices by hardware engineers have become more commonplace. In this article, we will discuss the differences between via in pad and traditional vias, when should you use via in pad, and how to design for it.
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