Electronics Forum | Sat Aug 22 12:18:12 EDT 1998 | Tryin'
| Board shops and us, the user, have a lot on our hands. As far as getting traces - this is done using an etch resist before solder mask and the HASL processes are performed. So when in the process is HASL performed?? | With tin/lead plated boards,
Electronics Forum | Thu Mar 28 15:53:49 EDT 2019 | SMTA-Jon
As a CM, we don’t have a lot of input on the PCB layouts we receive. Some engineers/software packages output the paste layer 1 to 1, some do an across the board reduction, and some set each part up individually with different reductions per footprin
Electronics Forum | Fri Jul 07 09:15:23 EDT 2000 | K. Chak
Hi Dave, This particular p/n calls for print&etch for wet process..and the problem occured due to surface contamin. with resist residue resisting copper from etching off. The high pressure nozzle was a problem at developing oper. and it is fixed now
Electronics Forum | Wed May 10 01:00:09 EDT 2000 | gary
0.65mm pitch QFP. I believe that this is the borderline for Fine Pitch. Will I have a good paste release with Chem-etch matched with a rubber squeegee? I'm planning of a 15% reduction on the Width and no reduction on the length. Any feedback whether
Electronics Forum | Thu Apr 25 18:32:25 EDT 2002 | Shawn
What he is talking about when he said "foil" is the top and bottom side of the board has a layer that is like a ground plane with no solder resist covering it. It is etched out around the pads that no not need a connection and have a small bride or t
Electronics Forum | Thu Jun 08 22:54:31 EDT 2006 | hunghung
Dear all, If a PCB board, 2 mils of core with 1oz copper at the top and bottom, is it a good board to be fabricated? will it be caused warpage during etching for inner layer process? if yes, what is the real factor caused to warpage? How to solve t
Electronics Forum | Tue Jun 03 01:03:04 EDT 2008 | daxman
Hi, I think what you are describing is a half-etch QFN, which causes the 3 mil gap. In our process, we don't require solder to bridge this gap as it's internally connected to the bottom lead. I'm not sure if this is the question you're asking, but
Electronics Forum | Fri Aug 22 14:24:54 EDT 2008 | boardhouse
Paul, I would do two things, eval whole lot for any etching issues as shown above and scrap and two I would have your copper thickness checked, my guess your copper plating will be low. Check plating thickness in Via holes - if less then 8/10th's r
Electronics Forum | Wed Jul 22 06:58:50 EDT 2015 | migliore
Hi, I got the answer from edaboard.com A standard 6-layer stack is using 2 cores. Manufacturing steps for standard 6-layer are: 1. Etch both (double side) core substrates 2. Assemble, press and cure the complete stack: - copper foil - prepr
Electronics Forum | Thu Feb 04 12:01:07 EST 2016 | g2garyg2
Hi Luis A white mask typically helps in the marking process since you are not reliant upon the PCB layers to create the contrast. Laser marking is really an etching process, so if your laser is set properly (power and focus) the goal with mask is to
