Electronics Forum: etl and testing (Page 7 of 30)

Lead Free and ICT

Electronics Forum | Tue May 09 14:49:57 EDT 2006 | Larry

Hey guys, Anybody having trouble with increased false contact issues in ICT after switching from lead to lead free? Our test guys keep trying to imply that the flux residues are a problem (we're using Alpha EF2202), but as the soldering process eng

Placement Accuracy and CPK

Electronics Forum | Tue May 22 16:07:31 EDT 2007 | francitj

We are doing a field study to test the placement accuracy and calculate cpk of some machines in our plant. From previous readings, it is suggested that you buy glass board kits from Accuspec, Topline, etc. Is that the easiest/cheapest way to go abo

Pick and Place Rivet

Electronics Forum | Wed Aug 13 09:20:05 EDT 2008 | wrongway

we tested this kind of part about 3 years ago did a few prototypes I did'nt know how it was going to work but our old amistar picked it and placed it just fine used a small nozzle with a o-ring on the end of it I think it did ok going across the wav

Tp9 and Tp9 ufp

Electronics Forum | Thu Oct 27 20:37:49 EDT 2011 | tech1

the calibration error sounds like it is an electrical verifier issue. Are you testing parts before you place them? It could be that your centering electrodes are worn or dirty, or it could be the ribbon cables from the centering unit. If you are usin

Re: IQ/OQ, and PQ

Electronics Forum | Wed Sep 15 11:08:45 EDT 1999 | Dave F

| I am looking for help on doing smt equipment qualifications. I need to find some examples to follow. The equipment to be qualified is a Stencil Machine, Pick and place machine, and Reflow oven. We manufacture medical devices so it has to be somewha

Spacing and Yield

Electronics Forum | Tue Sep 18 11:34:36 EDT 2001 | jschake

The tightest spacing between neighboring 0201 components assembled was 8-mils. Please refer to the response for the query entitled �Minimizing Tombstoning Defects� posted by martys, as the response provided there is also relevant to address this que

Dye and Pry

Electronics Forum | Wed Mar 12 23:00:10 EDT 2008 | davef

You can say: The pad was lifted after reflow and prior to the dye and pry failure analysis. When we see lifted pads, we think: * That's a good solder connection * Either it took a lot of force to lift that pad or the fabrication of the board in the

RNETs and Lead Free

Electronics Forum | Wed May 07 15:26:05 EDT 2008 | joeherz

Interesting - We're using the same AIM products as you. On the lead free, 353, did you start out with it or did you try the WS485? That was the 1st product recommendation we got from AIM and we found that the lot to lot consistency was not good. T

PCB Thickness and BLR

Electronics Forum | Mon Jun 03 13:26:32 EDT 2019 | az2019

Hi, I have a general question about the relationship of PCB thickness and BLR testing result. For example, I have QFN6x6 parts mounted on board in 1.2mm, 1.6mm, and 2.4mm thickness. All boards have 6 layers of Cu. Studies show thicker board gives les

AOI, Quality and SPC

Electronics Forum | Tue Mar 04 17:27:07 EST 2003 | msivigny

Hello Dave, I can understand why you might not use the auto-correct function based on the time it takes to perform the operation. I question why there is an auto-correct function in the first place? If I understand the way this works correctly, the m


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