Electronics Forum | Thu Sep 26 14:43:43 EDT 2002 | Jim M.
unsure of what solder spec. your working to?.IPC/EIA J-STD-001C, Section 9.2.4 clearly states dull, matte, gray or grainy appearing solders are accpetable depending on your process and if the acceptability of the neaxt paragraph is met.IPC 610 and J-
Electronics Forum | Thu Sep 26 11:44:23 EDT 2002 | abelardo
Hello everyone out there in the SMT world. I have a dilema I'm currently running a board that has 3 csp's with a .75 mm. ball pitch and .3mm ball size. And 2 qfp's-160. The stencil is 4 mils thick and I'm using a 63/37 solder paste. My reflow prof
Electronics Forum | Mon Jul 14 09:41:35 EDT 2008 | davef
Q1. Do we really need to follow the IPC J-STD-001 Solder purity? A1. Yes, you should control impurities in solder. Further information: * "Allowable concentration of contaminating elements in solder: impurities are harmless unless their level goes to
Electronics Forum | Thu Aug 10 13:16:17 EDT 2000 | Bob Willis
Here is some thing that I wrote a while back on solder beading. First what is a Solder Bead? The term solder bead is used to differentiate it from solder balls. A solder bead is a solder ball but its location is normally constant unlike solder bal
Electronics Forum | Fri Oct 06 15:43:33 EDT 2006 | Mario Scalzo, SMT CPE
What I usually do is keep the peak temperature about 5-10 deg C below the peak temperature of my lowest rated component, then set everything else up around that. Worse case scenario is to just extend the time above liquidus (TAL) in 5 second increme
Electronics Forum | Wed Feb 23 16:25:33 EST 2000 | John
We are using a glue and wave solder process for primarily chip components. Our products do not use any fine pitch components. What would an acceptable benchmark for the placement defect rate be? 50 DPMO? 100 DPMO? 200 DPMO? Thanks in advance,
Electronics Forum | Wed Feb 23 16:25:33 EST 2000 | John
We are using a glue and wave solder process for primarily chip components. Our products do not use any fine pitch components. What would an acceptable benchmark for the placement defect rate be? 50 DPMO? 100 DPMO? 200 DPMO? Thanks in advance,
Electronics Forum | Wed Jun 05 12:22:45 EDT 2002 | Bob
No. Placement force is fine. Also boards have been inspected prior to reflow using microscope with no evidance of misplaced solder balls. The ramp rate has been reduced to acceptable limits, typically .8 - 1.5 degrees per sec. Outgassing from eithe
Electronics Forum | Fri Sep 03 06:53:38 EDT 2010 | arjan
Yes, we assembled a lot of QFN in the last years, but we don't have a X-ray machine by ourself, so we cant't inspect each device. This type LGA was designed on a prototyping board of our customer so we would validate our LGA reflow process and a rese
Electronics Forum | Fri Jul 08 09:40:28 EDT 2005 | Jason Fullerton
"The only real problem we're seeing is some suppliers trying to use bismuth. That's a big no-no in a SnPb process and we won't accept those parts." Yes and no. Since the SnPbBi tertiary alloy melts at 96 degC, any product rated for storage above tha
