Technical Library: cogent and technology (Page 8 of 11)

Review of Interconnect Stress Testing Protocols and Their Effectiveness in Screening Microvias

Technical Library | 2016-11-30 15:53:15.0

The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology, the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated, the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that it is sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes, blind, or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly.

Raytheon

Making the Move from Machine Monitoring to SMART Manufacturing and the Implications on Profiling Systems

Technical Library | 2016-09-12 10:16:04.0

It is hard to open an Industry newsletter or visit an equipment manufacturer’s website without coming across a mention of the Internet of Things (IoT), Industry 4.0, SMART Manufacturing or ‘big data’. The accessibility to obtain data will only increase and this information and its real-time processing will become one of the most important resources for companies in the future. Production machinery will no longer simply processes the product, but the product will communicate with the machinery to tell it exactly what to do. Industry 4.0 has the vision to connects embedded system technologies and SMART production processes to drastically transform industry and production giving way to the SMART factory development. Future development in oven technology will allow machines to be controlled more intelligently and remotely resulting in the lowest cost model for manufacturing flow.

Solderstar

Copper/Epoxy Joints in Printed Circuit Boards: Manufacturing and Interfacial Failure Mechanisms

Technical Library | 2020-01-09 00:00:30.0

PCBs have a wide range of applications in electronics where they are used for electric signal transfer. For a multilayer build-up, thin copper foils are alternated with epoxy-based prepregs and laminated to each other. Adhesion between copper and epoxy composites is achieved by technologies based on mechanical interlocking or chemical bonding, however for future development, the understanding of failure mechanisms between these materials is of high importance. In literature, various interfacial failures are reported which lead to adhesion loss between copper and epoxy resins. This review aims to give an overview on common coupling technologies and possible failure mechanisms. The information reviewed can in turn lead to the development of new strategies, enhancing the adhesion strength of copper/epoxy joints and, therefore, establishing a basis for future PCB manufacturing.

Polymer Competence Center Leoben GmbH

Overview of Quality and Reliability Issues in the National Technology Roadmap for Semiconductors

Technical Library | 1999-08-05 10:27:43.0

This document is an update to the 1994 Quality and Reliability Roadmap issued in support of the 1994 National Technology Roadmap for Semiconductors. This report revisits the challenges, constraints, priorities, and research needs pertaining to quality and reliability issues. It also provides key project proposals that must be implemented to address concerns about reliability attainment and defect learning. An expanded section on test-to-test, diagnostics, and failure analysis; an edited version of the Product Analysis Forum Roadmap; and an appendix containing a draft report highlighting reliability issues is included.

SEMATECH

SMT Placement for ICs, Connectors and Odd-Shaped Components

Technical Library | 2009-11-18 23:37:52.0

Accurate component placement is a basic requirement for any pick and place machine. The first step towards accurate placement is accurate centering, or measurement of the component’s position on the placement head. One of the most widely used centering methods for ICs, connectors, and odd‐shaped components are a camera based system that measures the component position relative to a known point. Camera based centering systems include three main elements: lighting, camera, and software. Each of these elements are critical to obtaining an accurate measurement of the component and ultimately for accurate component placement on the PCB. As the old adage goes, the system is only as strong as its weakest link.

Juki Automation Systems

Package on Package (PoP) Stacking and Board Level Reliability, Results of Joint Industry Study

Technical Library | 2007-08-02 13:24:23.0

This paper presents the results of a joint - three way study between Amkor Technology, Panasonic Factory Solutions and Spansion in the area of package on package (PoP) board level reliability (BLR) (...) The scope of this paper is to cover the already popular 14 x 14mm PoP package size that provides a 152 pin stacked interface which supports a high level of flexibility in the memory architecture for multimedia requirements.

Amkor Technology, Inc.

Innovative Electroplating Processes for IC Substrates - Via Fill, Through Hole Fill, and Embedded Trench Fill

Technical Library | 2021-06-21 19:34:02.0

In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.

MacDermid Inc.

Issues and Challenges of Testing Modern Low Voltage Devices with Conventional In-Circuit Testers

Technical Library | 2012-12-14 14:25:37.0

The popularity of low voltage technologies has grown significantly over the last decade as semiconductor device manufacturers have moved to satisfy market demands for more powerful products, smaller packaging, and longer battery life. By shrinking the size of the features they etch into semiconductor dice, IC manufacturers achieve lower costs, while improving speed and building in more functionality. However, this move toward smaller features has lead to lower breakdown voltages and increased opportunities for component overstress and false failures during in-circuit test.

Teradyne

Challenges on ENEPIG Finished PCBs: Gold Ball Bonding and Pad Metal Lift

Technical Library | 2017-09-07 13:56:11.0

As a surface finish for PCBs, Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) was selected over Electroless Nickel/Immersion Gold (ENIG) for CMOS image sensor applications with both surface mount technology (SMT) and gold ball bonding processes in mind based on the research available on-line. Challenges in the wire bonding process on ENEPIG with regards to bondability and other plating related issues are summarized.

Teledyne DALSA

Design and Experiment of a Moving Magnet Actuator Based Jetting Dispenser

Technical Library | 2021-01-13 21:29:27.0

Developing actuators to drive high-frequency jetting dispensers in the dispensing technology for electronic assembly applications has become a concern in recent years. This study proposed a new jetting dispenser without a displacement amplification mechanism directly actuated by a moving magnet actuator (MMA) to jet small fluid droplets. In this article, the main geometric dimensions of ...

National Cheng Kung University


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