Electronics Forum: pad definition (Page 8 of 14)

Re: Voids in the joints

Electronics Forum | Mon Dec 22 16:02:22 EST 1997 | Justin Medernach

| what is your experience about the presence of the voids in the joints ? | Are they dangerous and when ? Vincenzo, Voids in solder joints can be caused by a number of factors. Let's begin with the flux vehicle in your soldering media. If the prope

Board Stretch...Is there a relevant IPC spec?

Electronics Forum | Wed Aug 22 19:54:54 EDT 2001 | mkallen

Can anyone point me to a relevant IPC spec that specifies an allowable board stretch, measured between metal features on outer layers (e.g., between fiducials and component pads on the topside of a board)? I've got a non-linear stretch problem that'

how to protect pads while applying solvent green mask? cure?

Electronics Forum | Wed Jun 18 07:49:06 EDT 2008 | more_sunshine

hi i'm not experienced in creating pcbs but i have good background, and i have a bunch of questions. i have no access to world wide known pcb chemicals but i managed to get a cramolin positiv spray and i don't know if it is still usable or not? (di

Re: BGA Shorting problem

Electronics Forum | Wed Sep 02 08:52:13 EDT 1998 | Justin Medernach

| | We are experiencing shorting on a BGA. The part has a 1mm pitch with a 196 I/O count. The problem seems to pop up without warning & disappear in the same manner. | | Our pad design is .020" diameter pads with .025" solder resist diameter. Th

Re: Tin-Lead thickness on PWB's/Let's Hear More

Electronics Forum | Tue May 26 14:50:07 EDT 1998 | Dave F

| | I'm reviewing my board fab spec. It calls for a minimum SnPb thickness of 50 microinches on HASL PWB's. I've looked at other specs that call out anything from 30 to 80 microinches, and others that just say the copper pad must be covered and sol

Re: Component Packaging Trends

Electronics Forum | Thu Oct 15 17:14:50 EDT 1998 | Justin Medernach

| Hi Folks, | As I travel our industry it seems to me the trend is to move from finner and finner pitch QFP's to array packages (BGA's, CSP's, etc.). Do you folks see the same trend? What is the finest pitch QFP package you have used in your process?

Re: IPC Land Pattern Vs Manufacturer's Recommendation

Electronics Forum | Wed Sep 06 11:18:52 EDT 2000 | Chris May

Randy, I have been with my present company about 14 months and my first and ongoing task is to improve 1st time yield rates at ATE. Upon examination of the failures (14 months ago)there were cases of IC legs being physically wider than the pads on

Re: Aperture Reduction for QFP (fine pitch)

Electronics Forum | Tue Sep 21 08:49:59 EDT 1999 | Chad Notebaert

| | My stencil thickness is 6 mil and we got qfp's with fine pitch. | | how many percent should i reduce my stencil aperture using a 6 mil stencil for 0.5 mm pitch and 0.4 mm pitch ? | | | | thanks | | | We use 6 mil lasercut stencils with 15% redu

Re: Cylindrical diodes Missing during SMT process.

Electronics Forum | Tue Aug 24 05:11:32 EDT 1999 | George Verboven

| | Hello everyone, | | We found many cylindrical diodes missing during SMT process. Could someone tell us how to prevent this problem? Is it effective to change the shape of stencil apture or reduce fan speed in reflow oven? Thanks in advance. | |

Re: the SOD-80 er the MELFs

Electronics Forum | Fri Jan 29 22:31:37 EST 1999 | Darren

| | | I am searching for application notes on the SOD-80. Also, I am looking for any problems that have been discovered while using it. Also, we are looking for the pick and place equipment upgrades that will be needed to use the package- Pricing,


pad definition searches for Companies, Equipment, Machines, Suppliers & Information