Electronics Forum | Fri May 17 20:11:32 EDT 2013 | isd_jwendell
I am familiar with TI's documents on QFN mounting. I do not have an X-Ray machine, so I worry about excessive voiding that could happen with using the thermal vias improperly. As a general rule-of-thumb, I print paste with a 25% reduction on the ther
Electronics Forum | Wed Mar 15 12:39:24 EDT 2017 | cyber_wolf
Customer precedes standard, but customer must be educated and informed on what is achievable with their design and what is accepted as industry standard practice. My guess is that the negative effect of those voids is negligible. {Voids at the sold
Electronics Forum | Wed Jul 18 17:09:45 EDT 2018 | slthomas
Update - next run started out horribly so went to another stencil design. Reduced thermal pad coverage by about 40% with 4 panes, with cutouts to avoid the vias. Worked like a charm for 10 boards (90 parts). I think we're finally on to something.
Electronics Forum | Mon Nov 12 09:22:41 EST 2007 | devajj
BTW, The surrounded QFN fine pitch terminals > should have the normal aperture reduction of 7 % > in case of RoHS Senju solder paste. This works > for our Telecom customer. > > The vias in the > ground pad will be somewhat filled with solder >
Electronics Forum | Wed Mar 15 04:36:16 EDT 2017 | Rob
@ Sr.Tech, Any voiding means that the part of the package under the void is not forming a solid thermal interface with the PCB, therefore it's heatsinking capability is reduced. With the drive for smaller packages with higher power handling capabil
Electronics Forum | Fri May 31 18:00:55 EDT 2013 | hegemon
With regards to first picture.(Large themal vias) I would attempt to measure the area of the ground pad, less the area of the "drain" holes or Thermal Vias. From that result I would reduce the aperture to account for about 50% coverage of that remai
Electronics Forum | Thu Nov 15 09:29:03 EST 2007 | jaimebc
Just to add to the subject, we experienced insufficient solder on our QFN's at our prototype level. To correct it, we went to a 5 mil stencil, 20% reduction on QFN pertures and used QFN's with solder bumps on the pads. We had great results using thi
Electronics Forum | Tue Aug 14 08:19:45 EDT 2018 | buckcho
Hello, other colleagues gave you valid ideas. I found it helpful if i reduce the size of the cooling openings. I would suggest making the four big square into very small many diamonds. This would maybe decrease your voiding with 2-4 percent. Btw how
Electronics Forum | Fri Dec 22 08:25:18 EST 2006 | aj
Hi, We had issues withthese parts when we first ran them thru our process. As the other lads have said - reduce thermal pad by 35-40%. ( we achieve this by using a dot matrix) . We also offset the lead apertures by 3thou ( i.e sort of overprinting)
Electronics Forum | Thu Mar 16 03:45:51 EDT 2017 | rob
It's the same thermal issue whether it's a die or package. It's different if it is just a signal trace, but if it's a heatsink pad (LED, FET, Motor driver, PSU IC etc). I think the voiding issue boils down to what the part is actually doing. The or
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