Electronics Forum | Fri May 02 09:37:23 EDT 2003 | Jerry Magera
Via in pad is the most efficient use of space. Blind via seems to be blamed for this. Cross-sections (send me some) will probably show a void still existing in the via or spherical voids aligned near the component pad side. One can estimate the vo
Electronics Forum | Mon Nov 26 23:05:05 EST 2001 | ianchan
M.Parker, thanks a million!
Electronics Forum | Thu Dec 06 19:46:08 EST 2001 | davef
First, we�re assuming that we�re talking hot air solder leveled [HASL] bare boards, eh? Consider using A-600 - Acceptability of Printed Boards as the basis for discussing the bare board problems. It is the bare board analog of A-610 - Acceptability
Electronics Forum | Mon Jan 07 13:18:28 EST 2002 | mregalia
I work for a microwave company. On our lower frequency boards (
Electronics Forum | Mon Jan 07 20:37:15 EST 2002 | davef
For soldered areas, we like to keep gold thickness substantially below the maximum you propose. Search the fine SMTnet Archives for our discussions on the topic of acceptable levels of gold with solder connections. Let�s fix this �no one seems be s
Electronics Forum | Wed Jan 16 20:05:04 EST 2002 | davef
Look here http://www.infoxpress.com/reviewtracker/reprints.asp?page_id=916
Electronics Forum | Thu Jan 24 09:53:56 EST 2002 | davef
You didn�t tell us about your solder, wave temperature profile, or the distribution of the problem. So, let�s assume the solder is near eutectic and the problem is wide spread. Wolfgang makes good points. So, let's talk a different tact. When we
Electronics Forum | Tue Feb 05 19:41:01 EST 2002 | PeteC
I sent you an e-mail with an attachment of a troubleshooting chart for wave and reflow.
Electronics Forum | Wed Feb 06 12:17:12 EST 2002 | cfraser
Could some one please send me a copy of the charts? It would be greatly appreciated.
Electronics Forum | Mon Feb 11 11:16:14 EST 2002 | cbarnett
I would also like to receive a copy of the chart. Thanks
