Technical Library | 2020-08-05 18:49:32.0
The evolution of internet-enabled mobile devices has driven innovation in the manufacturing and design of technology capable of high-frequency electronic signal transfer. Among the primary factors affecting the integrity of high-frequency signals is the surface finish applied on PCB copper pads – a need commonly met through the electroless nickel immersion gold process, ENIG. However, there are well-documented limitations of ENIG due to the presence of nickel, the properties of which result in an overall reduced performance in high-frequency data transfer rate for ENIG-applied electronics, compared to bare copper. An innovation over traditional ENIG is a nickel-less approach involving a special nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer. In this paper, assemblies involving this nickel-less novel surface finish have been subjected to extended thermal exposure, then intermetallics analyses, contact/sheet resistance comparison after every reflow cycle (up to 6 reflow cycles) to assess the prevention of copper atoms diffusion into gold layer, solder ball pull and shear tests to evaluate the aging and long-term reliability of solder joints, and insertion loss testing to gauge whether this surface finish can be used for high-frequency, high density interconnect (HDI) applications.
Technical Library | 2020-09-08 16:43:32.0
Atomic layer deposition (ALD) is an ultra-thin film deposition technique that has found many applications owing to its distinct abilities. They include uniform deposition of conformal films with controllable thickness, even on complex three-dimensional surfaces, and can improve the efficiency of electronic devices. This technology has attracted significant interest both for fundamental understanding how the new functional materials can be synthesized by ALD and for numerous practical applications, particularly in advanced nanopatterning for microelectronics, energy storage systems, desalinations, catalysis and medical fields. This review introduces the progress made in ALD, both for computational and experimental methodologies, and provides an outlook of this emerging technology in comparison with other film deposition methods. It discusses experimental approaches and factors that affect the deposition and presents simulation methods, such as molecular dynamics and computational fluid dynamics, which help determine and predict effective ways to optimize ALD processes, hence enabling the reduction in cost, energy waste and adverse environmental impacts. Specific examples are chosen to illustrate the progress in ALD processes and applications that showed a considerable impact on other technologies.
Technical Library | 2020-10-08 01:01:01.0
Flexible hybrid electronics (FHE) is emerging as a promising solution to combine the benefits of printed electronics and silicon technology. FHE has many high-impact potential areas, such as wearable applications, health monitoring, and soft robotics, due to its physical advantages, which include light weight, low cost and the ability conform to different shapes. However, physical deformations in the field can lead to significant testing and validation challenges. For example, designers must ensure that FHE devices continue to meet their specs even when the components experience stress due to bending. Hence, physical deformation, which is hard to emulate, has to be part of the test procedures for FHE devices. This paper is the first to analyze stress experience at different parts of FHE devices under different bending conditions. We develop a novel methodology to maximize the test coverage with minimum number of text vectors with the help of a mixed integer linear programming formulation. We validate the proposed approach using an FHE prototype and COMSOL Multiphysics simulations
Technical Library | 2021-02-17 22:41:48.0
This review provides an overview of electrochemical sensors for nitrogen species, especially, ammonium, nitrate, and nitrite. Due to the extensive anthropogenic activities, the concentration of nitrogen species has been dramatically increased in the environment. In particular, fertilizers containing ammonium and nitrate have been extensively used in agriculture where as nitrite-included additives or preservatives have been used in food industry. Since excessive nitrogen species have an adverse effect to environment and human health such as eutrophication and methemoglobinemia (blue baby syndrome), efforts have been made to develop efficient monitoring methods. On that account, the U.S Environmental Protection Agency (EPA) established the maximum contaminant level (MCL) for nitrate and nitrite to be 10mg/L nitrate-N and 1mg/L nitrite-N in drinking water, respectively. Typical analytical methods for nitrogen species are chromatography or spectrometry. However, these methods require expensive instrumentations, skilled operator, and considerable sample pretreatment and analysis time. As an alternative approach, electrochemical sensors have been explored to monitor nitrogen species owing to its simplicity, superior sensitivity, versatility, rapidity, field applicability, and selectivity. In this review, electrochemical based detection methods for nitrogen species especially ammonium, nitrate and nitrite are systematically discussed, including the fundamentals of electrochemical techniques, sensing mechanisms, and the performance of each sensor. doi.org/10.1016/j.snr.2020.100022
Technical Library | 2021-05-20 13:55:14.0
Quality Control is essential in production processes. In the PCB Assembly process there are several Quality Control steps or options. The most popular tests are the electrical (In-Circuit or ICT) and the function (functional or FCT/FVT) test. ICT test fixtures are standardized and there are several major test platforms available which are industry standards. For FCT applications there are many more variations possible due to the vast number of testers and interface approaches unique to each customer; also due to an endless list of applications which fall under the category of Functional Test (RF, High Current, LED test, Leak test etc.) Test Probes are a very important part in ICT as well as in FCT applications. If the wrong test probe (type, spring force, tip style etc.) is used, the test fixture will not work as intended. In addition the test probe must be installed correctly in order to work properly. This presentation will show general information and some guidelines for a proper Test Fixture design to assure the most efficient production.
Technical Library | 2021-06-02 19:34:48.0
In recent years, there has been dynamic changes in the industrial environment as a result of further innovations called Industry 4.0 (I.4.0), especially in the field of digital technology and manufacturing. Despite numerous examples of the implementation of Industry 4.0 in enterprises, there is no general framework for the implementation of Industry 4.0 with a detailed schedule. Researching the ways of implementing Industry 4.0 is still a current and unexplored area of research. The main aim of the paper is to present the concept of the theoretical framework for Industry 4.0 implementation based on selected schedules of the Industry 4.0 implementation. The paper was based on information from literature review and analysis of pilot enterprise projects to Industry 4.0 (case study) that were conducted in selected enterprises. The paper presents the key components of the framework of Industry 4.0 and the basic stage of implementing the concept in the enterprises, paying attention to their sequence and time frames. The proposed approach is dedicated to researchers and practitioners who implement the concept of Industry 4.0 in enterprises
Technical Library | 2023-06-12 18:33:29.0
This paper presents a real-time predictive approach to improve solder paste stencil printing cycle decision making process in surface mount assembly lines. Stencil cleaning is a critical process that influences the quality and efficiency of printing circuit board. Stencil cleaning operation depends on various process variables, such as printing speed, printing pressure, and aperture shape. The objective of this research is to help efficiently decide stencil printing cleaning cycle by applying data-driven predictive methods. To predict the printed circuit board quality level, a recurrent neural network (RNN) is applied to obtain the printing performance for the different cleaning aging. In the prediction model, not only the previous printing performance statuses are included, but also the printing settings are used to enhance the RNN learning. The model is tested using data collected from an actual solder paste stencil printing line. Based on the predicted printing performance level, the model can help automatically identify the possible cleaning cycle in practice. The results indicate that the proposed model architecture can predictively provide accurate solder paste printing process information to decision makers and increase the quality of the stencil printing process.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
Technical Library | 2016-04-14 13:49:44.0
A system level test, usually built-in test (BIT), determines that one or more subsystems are faulty. These subsystems sent to the depot or factory repair facility, called units under test (UUTs) often pass that test, an event we call No-Fault-Found (NFF). With more-and more electronics monitored by BIT, it is more likely that an intermittent glitch will trigger a call for a maintenance action resulting in NFF. NFFs are often confused with false alarm (FA), cannot duplicate (CNDs)or retest OK (RTOK) events. NFFs at the depot are caused by FAs, CNDs, RTOKs as well as a number of other complications. Attempting to repair NFF scan waste precious resources, compromise confidence in the product, create customer dissatisfaction, and the repair quality remains a mystery. The problem is compounded by previous work showing that most failure indications calling for repair action at the system level are invalid. NFFs can be caused by real failures or may be a result of system level false alarms. Understanding the cause of the problem may help us distinguish between units under test (UUTs) that we can repair and those that we cannot. In calculating the true cost of repair we must account for wasted effort in attempting to repair unrepairable UUTs.This paper will shed some light on this trade-off. Finally, we will explore approaches for dealing with the NFF issue in a cost effective manner.
Technical Library | 2021-06-07 19:03:05.0
The waste from end-of-life electrical and electronic equipment has become the fastest growing waste problem in the world. The difficult-to-treat waste-printed circuit boards (WPCBs), which are nearly 3−6 wt % of the total electronic waste, generate great environmental concern nowadays. For WPCB treatment and recycling, the mechanical−physical method has turned out to be more technologically and economically feasible. In this work, the mechanical−physical treatment and recycling technologies for WPCBs were investigated, and future research was directed as well. Removing electric and electronic components(EECs) from WPCBs is critical for their crushing and metal recovery; however, environmentally friendly and high-efficiency removal techniques need be developed. Concentrated metals rich in Cu, Al, Au, Pb, and Sn recovered from WPCBs need be further refined to add to their economic values. The low value added nonmetallic fraction of waste-printed circuit boards (NMF-WPCBs) accounts for approximately 60 wt % of the WPCBs. From the perspective of environmental management, a zero-waste approach to recycling them should be developed to gain values. Preparing polymer composites and geopolymers offers many advantages and has potential applications in various fields, especially as construction and building materials. However, the mechanical and thermal properties of NMF-WPCBs composites should be further improved for preparing polymer composites. Surface modification or filler blending could be applied to improve the interfacial comparability between NMF-WPCBs and the polymer matrix. The NMFWPCBs shows potential in preparing cement mortar and geological polymers, but the environmental safety resulting from metals needs to be taken into account. This study will provide a significant reference for the industrial recycling of NMF-WPCBs
