Technical Library | 2015-09-23 22:08:32.0
A molded interconnect device (MID) is an injection molded thermoplastic substrate which incorporates a conductive circuit pattern and integrates both mechanical and electrical functions. (...) Flip chip bonding of bare die on MID can be employed to fully utilize MID’s advantage in device miniaturization. Compared to the traditional soldering process, thermo-compression bonding with gold stud bumps provides a clear advantage in its fine pitch capability. However, challenges also exist. Few studies have been made on thermocompression bonding on MID substrate, accordingly little information is available on process optimization, material compatibility and bonding reliability. Unlike solder reflow, there is no solder involved and no “self-alignment,” therefore the thermo-compression bonding process is significantly more dependent on the capability of the machine for chip assembly alignment.
Technical Library | 2017-11-15 22:49:14.0
While a significant level of voiding can be tolerated in solder joints where electrical conductivity is the main requirement, voiding at any level severely compromises thermal conductivity. For example, in LED lighting modules effective conduction of heat through the 1st level die attach to the substrate and then through the 2nd level attach to the heat sink is critical to performance so that voiding in the solder joints at both levels must be minimized. (...) In this paper, the authors will review the factors that influence the incidence of voids in small and large area solder joints that simulate, respectively, the 1st and 2nd level joints in LED modules and discuss mitigation strategies appropriate to each level. They will also report the results of a study on the effect on the incidence of voids of flux medium formulation and the optimization of the thermal profile to ensure that most of the volatiles are released early in the reflow process.
Technical Library | 2018-12-19 21:23:59.0
With the rapid trend towards miniaturization in surface mount and MEMs lid-attach technology, it is becoming increasingly challenging to dispense solder paste in ultra-fine dot applications such as those involving chip capacitors or BGA packages, as well as dispensing ultra-fine lines in MEMs lid-attach applications. In order to achieve ultra-fine dots and fine line widths while dispensing solder paste, both the solder material and dispensing equipment need to be optimized. Optimizing the equipment can be very challenging, as there are many input variables that can affect the dispense quality of the solder paste. In this paper we will evaluate the many equipment variables involved in the solder paste dispensing process, and the impact these variables have on the dispense quality of the solder paste.
Technical Library | 2020-09-16 21:20:37.0
3D printing is disrupting the design and manufacture of electronic products. 3D printing electronics offers great potential to build complex object with multiple functionalities. Particularly, it has shown the unique ability to make embedded electronics, 3D structural electronics, conformal electronics, stretchable electronics, etc. 3D printing electronics has been considered as the next frontier in additive manufacturing and printed electronics. Over the past five years, a large number of studies and efforts regarding 3D printing electronics have been carried out by both academia and industries. In this paper, a comprehensive review of recent advances and significant achievements in 3D printing electronics is provided. Furthermore, the prospects, challenges and trends of 3D printing electronics are discussed. Finally, some promising solutions for producing electronics with 3D printing are presented.
Technical Library | 2021-12-16 01:48:41.0
Package-on-Package (PoP) technology is widely used in mobile devices due to its simple design, lower cost and faster time to market. Warpage characteristic and requirement of PoP package becomes critical to ensure both the top and bottom package can be mounted with minimal yield lost. With this challenge in placed, iNEMI has been working relentlessly to fingerprint the current PoP package technology warpage characteristic and to establish some key learning for packaging technologies. The work also extended to understand the basic requirement needed for successful PoP stacking by analyzing the warpage data obtained and formulate a simple analytical equation to explain the true warpage requirement for PoP packaging.
Technical Library | 2023-02-13 18:56:42.0
This paper describes the results of an intensive whisker formation study on Pb-free assemblies with different levels of cleanliness. Thirteen types of as-received surface-mount and pin-through-hole components were cleaned and intentionally contaminated with solutions containing chloride, sulfate, bromide, and nitrate. Then the parts were assembled on double-sided boards that were also cleaned or intentionally contaminated with three fluxes having different halide contents. The assemblies were subjected to high-temperature/high-humidity testing (85_C/85% RH). Periodic examination found that contamination triggered whisker formation on both exposed tin and solder fillets. Whisker occurrence and parameters depending on the type and level of contamination are discussed. Cross-sections were used to assess the metallurgical aspects of whisker formation and the microstructural changes occurring during corrosion.
Technical Library | 2023-06-14 01:09:26.0
In the electronic packaging industry, it is important to be able to make accurate predictions of board level solder joint reliability during thermal cycling exposures. The Anand viscoelastic constitutive model is often used to represent the material behavior of the solder in finite element simulations. This model is defined using nine material parameters, and the reliability prediction results are often highly sensitive to the Anand parameters. In this work, an investigation on the Anand constitutive model and its application to SAC solders of various Ag contents (i.e. SACN05, with N = 1, 2, 3, 4) has been performed. For each alloy, both water quenched (WQ) and reflowed (RF) solidification profiles were utilized to establish two unique specimen microstructures, and the same reflow profile was used for all four of the SAC alloys so that the results could be compared and the effects of Ag content could be studied systematically.
Technical Library | 2021-11-26 14:34:07.0
The use of desiccant bags filled with Silica Sand and or Clay beads used in conjunction with a Moisture Barrier Bag to control moisture for storage of printed circuit boards has long been an accepted practice and standard from both JEDEC and IPC organizations. Additionally, the use heated ovens for baking off moisture using the evaporation process has also been a long#2;standing practice from these organizations. This paper on alternative drying methods will be accompanied by completed independent, unbiased tests conducted by Vinny Nguyen, an engineering student (now graduated) from San Jose State University. The accompanied paper will examine the performance levels of different technologies of desiccant bags to control moisture in enclosed spaces. The tests and equipment set were reviewed by an engineer and consultant to the Lockheed Martin Aerospace Division and the IPC - TM-650 2.6.28 test method was review by engineer from pSemi. The tests were designed to mimic performance tests outlined in Mil Spec 3464, which both IPC and JEDEC have adopted for their respective standards. The test examined variables including absorption capacity rates, weight gain and release of moisture back into the enclosed area. The presentation will also address and highlight: • Similarities of PCBs and Heavy Equipment as it applies to Inspections, Causes of Failure, Types of Corrosion and Moisture Collection Points. • Performance Attributes of Different Desiccant Technologies as it applies to shape, texture, change outs, labeling and regeneration. • Venn Diagram of Electromechanical Failure with the circles 1. Current 2. Contamination 3. Humidity Presentation Available
Technical Library | 2018-10-18 15:41:45.0
One specific market space of interest to emerging printed electronics is In Mold Label (IML) technology. IML is used in many consumer products and white good applications. When combined with electronics, the In Mold Electronics (IME) adds compelling new product functionality. Many of these products have multi-dimensional features and therefore require thermoforming processes in order to prepare the labels before they are in-molded. While thermoforming is not a novel technique for IML, the addition of printed electronic functional traces is not well documented. There is little or no published work on printed circuit performance and design interactions in the thermoforming process that could inform improved IME product designs. A general full factorial Design of Experiments (DOE) was used to analyze the electrical performance of the conductive silver ink trace/polycarbonate substrate system. Variables of interest include trace width, height of draw, and radii of both top and bottom curvatures in the draw area. Thermoforming tooling inserts were fabricated for eight treatment combinations of these variables. Each sample has one control and two formed strips. Electrical measurements were taken of the printed traces on the polymer sheets pre- and post- forming with a custom fixture to evaluate the effect on resistance. The design parameters found to be significant were draw height and bottom radius, with increased draw and smaller bottom curvature radii both contributing to the circuits’ resistance degradation. Over the ranges evaluated, the top curvature radii had no effect on circuit resistance. Interactions were present, demonstrating that circuit and thermoforming design parameters need to be studied as a system. While significant insight impacting product development was captured further work will be executed to evaluate different ink and substrate material sets, process variables, and their role in IME.
Technical Library | 2020-07-02 13:16:32.0
Principle of shielding 1 The principle of shielding is creating a conductive layer completely surrounding the object you want to shield. This was invented by Michael Faraday and this system is known as a Faraday Cage. 2 Ideally, the shielding layer will be made up of conductive sheets or layers of metal that are connected by means of welding or soldering, without any interruptions. The shielding is perfect when there is no difference in conductivity between the used materials. When dealing with frequencies below 30 MHz, the metal thickness affects shielding effectiveness. We also offer a range of shielding methods for plastic enclosures. A complete absence of interruptions is not a realistic goal since the Faraday cage will have to be opened from time to time so electronics, equipment or people can be moved in or out. Openings are also needed for displays, ventilation, cooling, power supply, signals etc. 3 Shielding works in both directions, items inside the shielded room are shielded from outside influences. (Fig. 3.1)
