Contamination under chip resistor array

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We have experienced contamination under flat chip arrays. T... - Aug 20, 2008 by BR

Naw, accounting is boring. Standoff could be an issue. Co... - Aug 20, 2008 by davef

Thanks Dave, I will be sticking with Manufacturing Engineeri... - Aug 21, 2008 by BR

There is no standard as such. It's easy to see why. It's too... - Aug 21, 2008 by davef

#56080

Contamination under chip resistor array | 20 August, 2008

We have experienced contamination under flat chip arrays. The lab report is still open but it appears to be dendrite growth. We have been trouble-shooting our process and cleaning equipment.

My question is are there any specific design or best practices recommended for these types of packages? Are other folks challenged with these issues? We do not use them often so I don't have any experience to draw from.

I should have went into Accounting.

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davef

#56082

Contamination under chip resistor array | 20 August, 2008

Naw, accounting is boring.

Standoff could be an issue. Coupla things: * Above 30 thou, just about any cleaning process, more sophisticated than a garden hose, will produce acceptable results * Below 10 thou, can be cleaned with best efforts, but not with straight DI water * Between the 30 and 10 thou, can be cleaned with straight DI, but requires increased levels of process improvement, as the standoff decreases

Steve "Steve Zeva" Gregory recommended a method to help assess cleaning process improvements. [Although, he sugggested it as a tool to assess cleaner machine capability. He won't remember.] Look here: http://www.smtnet.com/forums/Index.cfm?CFApp=1&Message_ID=49244

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#56087

Contamination under chip resistor array | 21 August, 2008

Thanks Dave, I will be sticking with Manufacturing Engineering.

These are good guidelines but what is standard clearance for various packages? This is a dimension we usually seek by eye, whether we will have a problem or not.

We use straight DI - an old Treiber in-line system.

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davef

#56088

Contamination under chip resistor array | 21 August, 2008

There is no standard as such. It's easy to see why. It's too complicated and has such a small payoff. Standoff is comprised of: * Package height * Solder thickness between the pad and the component lead * Delta of pad thickness and solder mask

For package height, JEDEC developed package drawings for common semiconductors such as TO-3, TO-5, etc. Look here http://www.jedec.org/download/pub95/default.cfm

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