Line release of post reflow AOI and AXI

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Hello everyone! I'm a student of electrical engineering c... - Sep 16, 2008 by Ismir

> Hello everyone! > > I'm a student of electrica... - Sep 16, 2008 by Hegemon

Dear Hegemon, I'm very grateful for your help. There is o... - Sep 18, 2008 by Ismir

You are on the right track Ismir. Essentially however, as t... - Sep 22, 2008 by Hegemon

Ismir

#56533

Line release of post reflow AOI and AXI | 16 September, 2008

Hello everyone!

I'm a student of electrical engineering currently working on a thesis for my BSc degree. It will be about post reflow AOIs and AXIs, and I'd kindly like to ask you for some help with it.

I would like to know if there are any standards according to a line relase of an AOI/AXI for continous production, so basically - how do you test your machine? Do you do an (attribute) gauge R&R? Do you make bad samples for a test? How many, what failures? If there are any standards where can I read about them? If there are none please help me out: what do you guys do when you do a line release?

Thanks in advance, and please forgive my poor English, I'm not a native speaker.

Ismir

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Hegemon

#56546

Line release of post reflow AOI and AXI | 16 September, 2008

> Hello everyone! > > I'm a student of electrical > engineering currently working on a thesis for my > BSc degree. It will be about post reflow AOIs and > AXIs, and I'd kindly like to ask you for some > help with it. > > I would like to know if there > are any standards according to a line relase of > an AOI/AXI for continous production, so basically > - how do you test your machine? Do you do an > (attribute) gauge R&R? Do you make bad samples > for a test? How many, what failures? If there > are any standards where can I read about them? If > there are none please help me out: what do you > guys do when you do a line release? > > Thanks in > advance, and please forgive my poor English, I'm > not a native speaker. > > Ismir

I would like to know if there re any standards according to a line relase of an AOI/AXI for continous production, so basically - how do you test your machine? Ismir, I may be stepping in it here, but I am aware of no "standards" for implementation of post reflow AOI or AXI. I'm sure the brothers here will correct me if I am wrong.

Do you do an(attribute) gauge R&R? We do something similar. When setting up our AOI programs, we work with a "golden" PCB first when debugging the programs. Acceptance criteria are adjusted (matching scores)and the PCB is run through the machine repeatedly while adjusting acceptance criteria downward. At some point the machine interprets the artificial threshold and calls out a defect. Once this defect threshold has been established with the golden PCB, the PCB is run through the machine repeatedly to insure that the defect and defect rate is stable. In our evaluation of various machines we used 25 passes through the machine to gauge repeatability. The defect threshold is then raised to eliminate the defect, then the PCB is again run through the machine for 25 passes, and we expect to see no defects.

Do you make bad samples for a test? We do exactly that. Whatever soldering defect we are looking for, we use an existing PCB, and create to our best ability, an example of that type of defect. Solder bridge, incorrect polarity, component misalignment, missing part, extra part, insufficient solder, lifted lead, BGA planarity. These defects types are mapped onto a PCB and we again repeatedly run the PCB through the AOI machine to ensure the defect rate is stable.

How many, what failures? See above. In most cases the AOI machine has built in algorithms that will detect most defects using standard settings, fine tuning of the programs is where the artistry comes in.

Hope this is of some help to your questions.

'hege

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Ismir

#56584

Line release of post reflow AOI and AXI | 18 September, 2008

Dear Hegemon,

I'm very grateful for your help. There is one more thing that I'd like to discuss with you.

I'd like to know if there is any "verification board" or something like that to check if you really did a good job. At the company where I work, engineers fine-tune the machine like you said, and when they are ready, their boss comes to test the machine with his own PCB(s) (prepared by himself in a secret top lab:P) that has a few artificially prepared errors. Is there something like that there too? If there is, what is the preferred logic when making a superboard like this?

Is it to do as many types of mistakes as possible? Is it the number of mistakes? Or is the goal to "trick" the machine with marginal errors? Or maybe aiming for the simulation of real errors would be preferable?

The great question here is: if you could make a "superboard" like this, what would it be like and why?

Thanks again!

Ismir

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Hegemon

#56631

Line release of post reflow AOI and AXI | 22 September, 2008

You are on the right track Ismir. Essentially however, as the programmer of the machine, I am the one that creates the PCB with the errors to benchmark the settings for the machine. No secret lab though! :-) Easy enough for most any AOI machine to catch a solder bridge, polarity or alignment problem. Less so with things such as lifted lead, or solder volume at individual pads. Our machines have lasers to deal with coplanarity and lifted leads, but what I am saying is this:

This is over simplified, but since the machines are for the most part comparators, the logic is that it is comparing a "golden" picture (from programming with a gold board) to a new picture (what is being inspected). Comparisons are made at defined locations, and reflected light (and the amount of it) becomes the measuring medium. So the comparison is by pixel count, and in some machines, pixel coloration. Again, easy enough to find obvious problems right out in the open. For us, however, we have component locations such that the inspection area is actually in the "shadow" of another component. It is in these locations where fine tuning of the program is essential, for example, solder inspection of a QFP where one bank of leads is in shadow. The normal settings for that type of component will not give you consistent results if the part is shadowed on one side or another.

I do not try to incorporate huge numbers of errors into my test PCBs, but I do try to induce as many different TYPES of defects including solder splash, solder balls, extra component, missing component, bridging, polarity, incorrect part #(for OCR)

As far as tricking the machine with marginal errors, I suppose you could describe it that way, but I think of it more as providing a worst case scenario for the machine to interpret, and since I know the extent of the defects, it becomes easier to "tune " the programs up should the machine not catch defects as you sharpen up the passing scores.

Hope this is of some help.

'hege

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