Question of delamination in PCB

#58705

Question of delamination in PCB | 1 May, 2009

In my project of flip chip PGA production , I found serious delamination in interface of solder mask and first layer copper trace of substrate after UHAST 96hrs( 130C, 85%RH) reliability test. The delamination are always around one type solder bump, and there is tin diffusion on copper trace surface issue. I am puzzle it and want to get a reasonable explain about the delamination and tin diffusion.

Is there any idea about it?

Attachments:

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#58715

Question of delamination in PCB | 2 May, 2009

You have a board defect. Any moisture and/or organic contaminants trapped by the solder resist during lamination may cause solder mask delamination, blistering and/or adhesion loss during subsequent soldering operations or during extended use.

#58716

Question of delamination in PCB | 2 May, 2009

Thanks davef.

The defect always occurred during UHAST reliability, but not find in reflow. The key is that there is tin diffuse to copper trace under solder mask. is it a "normal" board defect and what is the potential risk for device? thanks!

#58740

Question of delamination in PCB | 7 May, 2009

any other suggestion for it?

#58741

Question of delamination in PCB | 7 May, 2009

We don't have a good answer for you, but we do have several thoughts on the issue: * First, tin in your solder or solderability protection is going to diffuse into the copper trace or pad on the board naturally. You can stop that by using a protective layer of plating between the copper and tin plating. Nickel is often used as a protective plating. * Second, we wonder how well your UHAST 96hrs( 130C, 85%RH) reliability test represents product use. See ANSI/IPC-SM-785 Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments

#58746

Question of delamination in PCB | 7 May, 2009

Hi Davef,

Do you means it is natural for tin diffusion to copper trace during SMT process? but I could not detect tin in UHAST T=0 unit, and the tin diffusion was found only in copper trace of C4 cage. Two question: 1) Could you tell me which process have risk to cause it? 2) what is the potential risk for tin diffusion to copper trace?

BTW, in my company, JEDEC standard JESD22-A118 is performed for new product qualification.

#58747

Question of delamination in PCB | 7 May, 2009

From our notes, the following is a series of snips from: "Copper Dissolution in Tin" LJ Turbini, PhD, adjunct faculty member, University of Toronto, Materials Science and Engineering, SMT 2/07

As the solder becomes molten, copper from the board diffuses into the solder, while tin from the solder diffuses into the copper. Finally, the molten solder solidifies - leaving a copper-tin intermetallic at the interface that acts as the bond or glue, holding the solder and copper together.

In the lead-free soldering era, the percentage of tin (Sn) in new solder alloys is 95-99%, far greater than the 63% in traditional eutectic tin/lead. At the higher tin concentration, the amount of copper diffusing into the solder from pads, microvias, and plated holes will be two to four times as much as it will be for tin/lead.

In this lead-free world, the copper-diffusion problem will limit the number of times an assembly can be reworked. Once the copper trace, knee, or microvia has dissolved completely into the solder, electrical interconnections and product reliability are compromised.

Refernces on copper diffusion * �Effect of Lead-free Soldering on Plating Vias" J Fellman, Proceedings of International Conference on Lead-free Soldering, Toronto, Ontario, May 2006. * �A Study of Copper Dissolution During Lead Free PTH Rework Using a Thermally Massive Test Vehicle� C Hamilton, P Snugovsky & M Kelly, SMTAI 2006 Proceedings, p177. * �A Study of Copper Dissolution in Lead-free Solder Fountain Systems,� F Byle, D Jean & D Lee, SMTAI 2006 Proceedings, p183. * International Electronics Manufacturing Initiative http://www.inemi.org.

We understand that your company has a policy on new product qualification. On the surface of things, JEDEC JESD22-A118 seems to be a poorly selected test for a printed circuit board. According to the stated purposed of the test, it's intended for "non-hermetic packaged solid-state devices." See below: JEDEC JESD22-A118, UHAST (Unbiased Highly Accelerated Temperature and Humidity Stress Test): "The Unbiased HAST is performed for the purpose of evaluating the reliability of non-hermetic packaged solid-state devices in humid environments. It is a highly accelerated test which employs temperature and humidity under non-condensing conditions to accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors which pass through it. Bias is not applied in this test to ensure the failure mechanisms potentially overshadowed by bias can be uncovered (e.g. galvanic corrosion). This test is is used to identify failure mechanisms internal to the package and is destructive." http://www.jedec.org/download/search/22a118.pdf

#58750

Question of delamination in PCB | 8 May, 2009

Hi Davef,

I want to explain that the tin diffusion in my project is not on solder bump/Pad region. It is on copper trace between bumps. so it is very wondering for me.

#58751

Question of delamination in PCB | 8 May, 2009

Board fabricators use solder as a resist to protect copper traces from process chemicals. Fabricators remove this resist in later processing.

It's possible that board fabrication processing is the source of the tin that you see.

#58755

Question of delamination in PCB | 8 May, 2009

Davef,

do you have some information about your mention "tin was used to protect copper trace ans will be removed"?

It is very important for my project. Because we are assy and test plant, no any information from PCB vendor.

Thanks!

#58757

Question of delamination in PCB | 8 May, 2009

X-section image: tin layer on top of copper trace.

Attachments:

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#58758

Question of delamination in PCB | 9 May, 2009

For more on using tin as a resist during bare board fabrication, read "2.5.6 Introduction To Tin And Tin/Lead Plating" here: http://books.google.com/books?id=etfNcpiR5ZUC&pg=PT570&lpg=PT570&dq=%22circuit+board%22+%22etch+resist%22+%22acid+sulfate%22&source=bl&ots=ZfXThtg-Uo&sig=zGQ9Voyg0HXUeAOM1Gtg2Q8fK40&hl=en&ei=tH0FSuetMIaEtwe5-5SMBw&sa=X&oi=book_result&ct=result&resnum=2

#58759

Question of delamination in PCB | 9 May, 2009

The whitish tin layer and the solder mask appear to be incompatible, resulting in adhesion loss.