Qualifying new PWB Vendors

Hello,

We are qualifying new sources of PWB vendors. We've got the first lot of "produciton" boards in and we want to put them through the paces before turing the vendors on.

So far, the tests I can think of performing, and that we have the capability to perform are: 1) Dimensional stability (we have an OGP non-contact CMM) 2) Plating thickness (we have x-section and XRF) 3) Solder wetting (run over the wave without nitrogen) 4) Solder mask peel test (need a little help here - I belive it involves scotch tape getting pulled at 90 degrees to the plane of the board) 5) Run the lot through the line and look for anything unusual (sounds kind of lame, doesn't it?)

What else sohuld I run before turning this vendor on for full bore production? (You out there today, Moon Man? Your expertise is needed on this one.)

Any and all input is appreciated.

Chrys

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| Hello, | | We are qualifying new sources of PWB vendors. We've got the first lot of "produciton" boards in and we want to put them through the paces before turing the vendors on. | | So far, the tests I can think of performing, and that we have the capability to perform are: | 1) Dimensional stability (we have an OGP non-contact CMM) | 2) Plating thickness (we have x-section and XRF) | 3) Solder wetting (run over the wave without nitrogen) | 4) Solder mask peel test (need a little help here - I belive it involves scotch tape getting pulled at 90 degrees to the plane of the board) | 5) Run the lot through the line and look for anything unusual (sounds kind of lame, doesn't it?) | | What else sohuld I run before turning this vendor on for full bore production? (You out there today, Moon Man? Your expertise is needed on this one.) | | Any and all input is appreciated. | | Chrys | | One of the best books on the subject of inspection and quality control was written by my good friend Preben Lund Quality Assesment of PCB which may be of value. It was published in 1986 by Bishop Graphics in California and is one of my all time top ten.

This will tell you what to look for but more inportant how to do it. |

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| Hello, | | We are qualifying new sources of PWB vendors. We've got the first lot of "produciton" boards in and we want to put them through the paces before turing the vendors on. | | So far, the tests I can think of performing, and that we have the capability to perform are: | 1) Dimensional stability (we have an OGP non-contact CMM) | 2) Plating thickness (we have x-section and XRF) | 3) Solder wetting (run over the wave without nitrogen) | 4) Solder mask peel test (need a little help here - I belive it involves scotch tape getting pulled at 90 degrees to the plane of the board) | 5) Run the lot through the line and look for anything unusual (sounds kind of lame, doesn't it?) | | What else sohuld I run before turning this vendor on for full bore production? (You out there today, Moon Man? Your expertise is needed on this one.) | | Any and all input is appreciated. | | Chrys | | | Chrys,

What timing! I'm just finishing up my latest, lamest, and "greatest" article for PC Fab concerning this very issue. So glad you asked us.

If you haven't already, it's now too late, always hang quality conformance test circuitry on your panels per IPC design standards. All test functions may be performed with individual test coupons as part of the circuitry. Included are tests as received and after thermal stress and shock (A and B coupons respectively), solder mask testing (not with tape pull test required for plating adhesion only), continuity, dielectric withstanding voltage, hole wall preparation, etch back/smear removal, plating quality and thickness, dielectric and conductor thickness, impedance, shorting, and so much more.

Most improtant, whether you have test circuitry or not, besides solder wetting is hole wall and laminate integrity after thermal stress. And on it goes.

May article primarily deals with two supplier/PCB evaluation and qualification issues. One is how defect is prevented by suppliers managing processes instead of reacting to defect as results of poor process management. A major part of this evaluation is done simply by what type and how well the laboratory is managed and what ads are made when, etc. The other deals with the lab's x-sectional analysis capabilities.

I mean, what goes into the product is first looked at in the lab, and effects concerning what goes in and how well the process is managed is looked at mostly in x-section. After all, 90% of your MLB is in the z axis.

There's more, but even if you don't currently hang coupons on every panel, you have the capability to cut up perfectly good boards.

Enjoy,

Earl Moon

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| | Hello, | | | | We are qualifying new sources of PWB vendors. We've got the first lot of "produciton" boards in and we want to put them through the paces before turing the vendors on. | | | | So far, the tests I can think of performing, and that we have the capability to perform are: | | 1) Dimensional stability (we have an OGP non-contact CMM) | | 2) Plating thickness (we have x-section and XRF) | | 3) Solder wetting (run over the wave without nitrogen) | | 4) Solder mask peel test (need a little help here - I belive it involves scotch tape getting pulled at 90 degrees to the plane of the board) | | 5) Run the lot through the line and look for anything unusual (sounds kind of lame, doesn't it?) | | | | What else sohuld I run before turning this vendor on for full bore production? (You out there today, Moon Man? Your expertise is needed on this one.) | | | | Any and all input is appreciated. | | | | Chrys | | | | | | | Chrys, | | What timing! I'm just finishing up my latest, lamest, and "greatest" article for PC Fab concerning this very issue. So glad you asked us. | | If you haven't already, it's now too late, always hang quality conformance test circuitry on your panels per IPC design standards. All test functions may be performed with individual test coupons as part of the circuitry. Included are tests as received and after thermal stress and shock (A and B coupons respectively), solder mask testing (not with tape pull test required for plating adhesion only), continuity, dielectric withstanding voltage, hole wall preparation, etch back/smear removal, plating quality and thickness, dielectric and conductor thickness, impedance, shorting, and so much more. | | Most improtant, whether you have test circuitry or not, besides solder wetting is hole wall and laminate integrity after thermal stress. And on it goes. | | May article primarily deals with two supplier/PCB evaluation and qualification issues. One is how defect is prevented by suppliers managing processes instead of reacting to defect as results of poor process management. A major part of this evaluation is done simply by what type and how well the laboratory is managed and what ads are made when, etc. The other deals with the lab's x-sectional analysis capabilities. | | I mean, what goes into the product is first looked at in the lab, and effects concerning what goes in and how well the process is managed is looked at mostly in x-section. After all, 90% of your MLB is in the z axis. | | There's more, but even if you don't currently hang coupons on every panel, you have the capability to cut up perfectly good boards. | | Enjoy, | | Earl Moon | Sure wish I could remember all I forgot. What I forgot this time, but remembered, is ductility. One of the really most important tests your new supplier must run, to be qualified to my standards, is tensile and eleongation. They analyze and maintain their plating solutions, therefore they must make dogbones and stick them in the clamps and stretch them. If the plating is as specified, the ductility will not be less than 20% (my spec) and often reaches 30%. This is especially important in high aspect ration plated through noles we've all come to know and love.

Earl Moon

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Hey Ya' Chrys!!

One other thing I can think of when it comes to looking at FAB vendors to rate how good they are, might be something that you may not be too concerned with (depending on the product you build), is their scoring capability. If you do a lot of panels, good scoring is important....there was a FAB vendor we quit doing business with when I was at Smart Modular because of the crappy score jobs we seemed to get all the time. Either the panels were scored too deep and fell apart before we finished building them, or it wasn't scored deep enough, setting us up for a bunch of fractured solder joints if we didn't catch the problem before depaneling.

But, you may not need that capabilty...just thought I'd give you a little tip from experience.

C-ya L8'ter!

-Steve Gregory-

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| | | Hello, | | | | | | We are qualifying new sources of PWB vendors. We've got the first lot of "produciton" boards in and we want to put them through the paces before turing the vendors on. | | | | | | So far, the tests I can think of performing, and that we have the capability to perform are: | | | 1) Dimensional stability (we have an OGP non-contact CMM) | | | 2) Plating thickness (we have x-section and XRF) | | | 3) Solder wetting (run over the wave without nitrogen) | | | 4) Solder mask peel test (need a little help here - I belive it involves scotch tape getting pulled at 90 degrees to the plane of the board) | | | 5) Run the lot through the line and look for anything unusual (sounds kind of lame, doesn't it?) | | | | | | What else sohuld I run before turning this vendor on for full bore production? (You out there today, Moon Man? Your expertise is needed on this one.) | | | | | | Any and all input is appreciated. | | | | | | Chrys | | | | | | | | | | | Chrys, | | | | What timing! I'm just finishing up my latest, lamest, and "greatest" article for PC Fab concerning this very issue. So glad you asked us. | | | | If you haven't already, it's now too late, always hang quality conformance test circuitry on your panels per IPC design standards. All test functions may be performed with individual test coupons as part of the circuitry. Included are tests as received and after thermal stress and shock (A and B coupons respectively), solder mask testing (not with tape pull test required for plating adhesion only), continuity, dielectric withstanding voltage, hole wall preparation, etch back/smear removal, plating quality and thickness, dielectric and conductor thickness, impedance, shorting, and so much more. | | | | Most improtant, whether you have test circuitry or not, besides solder wetting is hole wall and laminate integrity after thermal stress. And on it goes. | | | | May article primarily deals with two supplier/PCB evaluation and qualification issues. One is how defect is prevented by suppliers managing processes instead of reacting to defect as results of poor process management. A major part of this evaluation is done simply by what type and how well the laboratory is managed and what ads are made when, etc. The other deals with the lab's x-sectional analysis capabilities. | | | | I mean, what goes into the product is first looked at in the lab, and effects concerning what goes in and how well the process is managed is looked at mostly in x-section. After all, 90% of your MLB is in the z axis. | | | | There's more, but even if you don't currently hang coupons on every panel, you have the capability to cut up perfectly good boards. | | | | Enjoy, | | | | Earl Moon | | | Sure wish I could remember all I forgot. What I forgot this time, but remembered, is ductility. One of the really most important tests your new supplier must run, to be qualified to my standards, is tensile and eleongation. They analyze and maintain their plating solutions, therefore they must make dogbones and stick them in the clamps and stretch them. If the plating is as specified, the ductility will not be less than 20% (my spec) and often reaches 30%. This is especially important in high aspect ration plated through noles we've all come to know and love. | | Earl Moon | Thanks, Earl. I knew you'd come through. Let me ask you a few questions about your response:

I think we have an old ESS chamber kicking around here somewhere. What cycle (time, temp, qty) would be appropriate for thermal stress tests?

Tensile and elongation tests: I can't decipher from your writing whether you mean that the supplier should cast dogbones from the plating solution and run tensile tests or if the samples would be cut from a fab and have the plating inspected for damage after elongation.

Finally, what is the deal with the mask adhesion test and tape? Our engineer here said we are getting dry film instead of LPI. Is this a concern?

Thanks again.

reply »

| | | | Hello, | | | | | | | | We are qualifying new sources of PWB vendors. We've got the first lot of "produciton" boards in and we want to put them through the paces before turing the vendors on. | | | | | | | | So far, the tests I can think of performing, and that we have the capability to perform are: | | | | 1) Dimensional stability (we have an OGP non-contact CMM) | | | | 2) Plating thickness (we have x-section and XRF) | | | | 3) Solder wetting (run over the wave without nitrogen) | | | | 4) Solder mask peel test (need a little help here - I belive it involves scotch tape getting pulled at 90 degrees to the plane of the board) | | | | 5) Run the lot through the line and look for anything unusual (sounds kind of lame, doesn't it?) | | | | | | | | What else sohuld I run before turning this vendor on for full bore production? (You out there today, Moon Man? Your expertise is needed on this one.) | | | | | | | | Any and all input is appreciated. | | | | | | | | Chrys | | | | | | | | | | | | | | | Chrys, | | | | | | What timing! I'm just finishing up my latest, lamest, and "greatest" article for PC Fab concerning this very issue. So glad you asked us. | | | | | | If you haven't already, it's now too late, always hang quality conformance test circuitry on your panels per IPC design standards. All test functions may be performed with individual test coupons as part of the circuitry. Included are tests as received and after thermal stress and shock (A and B coupons respectively), solder mask testing (not with tape pull test required for plating adhesion only), continuity, dielectric withstanding voltage, hole wall preparation, etch back/smear removal, plating quality and thickness, dielectric and conductor thickness, impedance, shorting, and so much more. | | | | | | Most improtant, whether you have test circuitry or not, besides solder wetting is hole wall and laminate integrity after thermal stress. And on it goes. | | | | | | May article primarily deals with two supplier/PCB evaluation and qualification issues. One is how defect is prevented by suppliers managing processes instead of reacting to defect as results of poor process management. A major part of this evaluation is done simply by what type and how well the laboratory is managed and what ads are made when, etc. The other deals with the lab's x-sectional analysis capabilities. | | | | | | I mean, what goes into the product is first looked at in the lab, and effects concerning what goes in and how well the process is managed is looked at mostly in x-section. After all, 90% of your MLB is in the z axis. | | | | | | There's more, but even if you don't currently hang coupons on every panel, you have the capability to cut up perfectly good boards. | | | | | | Enjoy, | | | | | | Earl Moon | | | | | Sure wish I could remember all I forgot. What I forgot this time, but remembered, is ductility. One of the really most important tests your new supplier must run, to be qualified to my standards, is tensile and eleongation. They analyze and maintain their plating solutions, therefore they must make dogbones and stick them in the clamps and stretch them. If the plating is as specified, the ductility will not be less than 20% (my spec) and often reaches 30%. This is especially important in high aspect ration plated through noles we've all come to know and love. | | | | Earl Moon | | | Thanks, Earl. I knew you'd come through. Let me ask you a few questions about your response: | | I think we have an old ESS chamber kicking around here somewhere. What cycle (time, temp, qty) would be appropriate for thermal stress tests? | | Tensile and elongation tests: I can't decipher from your writing whether you mean that the supplier should cast dogbones from the plating solution and run tensile tests or if the samples would be cut from a fab and have the plating inspected for damage after elongation. | | Finally, what is the deal with the mask adhesion test and tape? Our engineer here said we are getting dry film instead of LPI. Is this a concern? | | Thanks again. | Chrys,

After all the help you've provided us all, it's a privelage to help you in some small/big way.

The tensile and elongation testing must be done by your supplier as part of your evaluation of its capabilities. Simply, a standard "dogbone" is imaged on a plated up (2oz Cu) very polished stainless steel plate (several dog bones per plate per bath). After imaging, the pattern is stripped and removed for testing. You should be allowed access to test results in the areas I've previously discussed.

Another way you, and your prospective board shops, may determine acceptable ductility is through the thermal stress and shock testing I mentioned. This really is a simple process wherein a test coupon (B) is removed and pre-conditioned (thermal stress) as you would expect in wave and reflow processing (it's a simulation test) and then placed on a solder pot (floated) for 10 seconds at 550 degrees F. You don't use an oven except to pre-condition the specimen. For thermal shock, you don't pre-conditiont the specimen - just go to the float.

This testing, in conjunction with the fabricators ductility testing, provides imperical evidence plated hole wall failure will not occur, nor will laminate voids propagate into the hole wall causing opens.

As for your solder mask, I'm very sorry to hear you are using DF. This stuff was supposed to be "banned" by everyone but Saddam. If you can, go to LPI. If not, there is no test to determine adhesion as no cure or molecular x-linking occurs with DF to the substrate's surface. It either works or it doesn't and it doesn't but provides never ending solder balls - unlike LPI.

For detailed information concerning all the above and more, address IPC-D-275 (now, I believe, 2221 and 2222) for quality conformance test circuitry requirements. For evaluation and qualification testing, use the old MIL-P-55110 or its new equivalents 6012 and 6013. For test requirements, procedures, and methods, hire me or, better yet, call an independent military or industry test laboratory nearest you.

You've seen a neat lady, representing Robisan test labs. She's a good place to start or go to Trace, Delsen, or Pacific labs for more information.

I'm really glad to be of service on this one because we all tend to get away from one of the most important basics, without which we would have no industry, the basic PCB.

Go get 'em,

Earl

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| Hello, | | We are qualifying new sources of PWB vendors. We've got the first lot of "produciton" boards in and we want to put them through the paces before turing the vendors on. | | So far, the tests I can think of performing, and that we have the capability to perform are: | 1) Dimensional stability (we have an OGP non-contact CMM) | 2) Plating thickness (we have x-section and XRF) | 3) Solder wetting (run over the wave without nitrogen) | 4) Solder mask peel test (need a little help here - I belive it involves scotch tape getting pulled at 90 degrees to the plane of the board) | 5) Run the lot through the line and look for anything unusual (sounds kind of lame, doesn't it?) | | What else sohuld I run before turning this vendor on for full bore production? (You out there today, Moon Man? Your expertise is needed on this one.) | | Any and all input is appreciated. | | Chrys | | | Chrys,

Thought you, and some others, might be interested in an actual thermal stress procedure I implement and use in the PCB and independent test laboratories I setup

7.2 THERMAL STRESS Thermal stress testing is required to verify laminate and hole wall integrity. If delamination occurs or propagates into the plated through hole wall, electrical continuity will be discontinued. Also, if insufficient plating ductility is found, during thermal stress testing, electrical continuity will be discontinued. The following documents, and requirements shall be referenced, and used in actual operations:

7.2.1 Applicable Documentation MIL-P-55110D, Paragraphs 3.5.3, 3.9, 3.9.1, 4.8.1, 4.8.1.2, 4.8.1.2.1, 4.8.6.1 Figure 8.

7.2.2 Apparatus, Equipment, And Materials Solder Pot (12" X 4") or round 8" Dia. RMA, Water Soluble Flux Desiccator Insulator Stainless Steel Tongs 10X Eye Loupe Soft Bristle Brush Optical Microscope Ten Second Timer

7.2.3 Procedures The test specimen shall be preconditioned in a laboratory oven, for a minimum of 2 hours, at 250 degrees F. After conditioning, the specimen shall be placed in a desiccator for approximately 40 minutes to cool to room temperature.

7.2.3.1 Fluxing After The Cooling Process, the specimen shall be immersed in a RMA type water soluble flux conforming to MIL-F-14256. The specimen shall be allowed to drain in a vertical position for 1 minute.

7.2.3.2 Solder Floating The Solder Pot shall be programmed to maintain a temperature of 550 degrees F + 10 degrees F. Using stainless steel tongs, the fluxed specimen shall be held horizontally over the solder immediately before floating. The specimen shall then be placed onto the surface of the molten solder, and allowed to float for 10, +1 - 0 seconds with the operator observing the ten second timer. When the specified time has elapsed, the specimen shall be removed from the solder, and held still, in a horizontal position, for 15 seconds, above the solder pot until solder has solidified. The specimen shall then be placed on an insulator, and allowed to cool to room temperature.

7.2.3.3 Visual Examination The specimen shall be cleaned with water to remove water soluble flux residue. After cleaning, the specimen shall be examined with a 10X Eye Loupe for "subsurface imperfections" such as, blistering, and delamination. Surface solderability also shall be observed. Note: The specimen shall then be microsectioned in accordance with the microsection procedures of this document.

7.2.3.4 Microstructural Examination The plated-through holes of the microsection shall be examined with an optical microscope, in accordance with Figure 8 (P-T-H Structure evaluation zones) of POD, or MIL-P-55110D. Figure 8 exhibits a typical cross sectional view of 3 plated-through holes after having been subjected to stress conditions, delineating the LAMINATE EVALUATION AREA (Zone "B"), and the FOIL" and PLATING EVALUATION AREA (Zone "A"). Material, and plating quality characteristics shall be observed, and shall not exhibit:

SEPARATION OF PLATING AND CONDUCTORS. CRACKING IN THE INTERNAL CONDUCTIVE FOIL, PLATING OR COATINGS. LIFTED LANDS EXCEEDING 0.003" WITH LESS THAN A 50% BOND TO THE SUBSTRATE MATERIAL. MEASLING EXCEEDING REQUIREMENTS OF IPC-A-600, CLASS 3. SUBSURFACE IMPERFECTIONS EXCEEDING THOSE SPECIFIED EVIDENCE OF OUTGASSING.

Notes: Laminate voids shall not be evaluated in Zone A (Thermal Zone). Laminate voids greater than 0.003" that extend into Zone B (laminate evaluation area) are REJECTABLE. Cracks shall be permissible in the outer copper foil if they do not extend into the plated copper. Resin recession at the outer surface of the plated-through hole barrel shall be permitted and is not caused for rejection.

Zone A shall be designated as the area encompassing the plated-through hole; extending 0.003" maximum beyond the land most radially extended.

The plated-through holes of the microsection shall be examined with an optical microscope, in accordance with Figure 8 (P-T-H Structure evaluation zones) in MIL-P-55110D and figure 7 in POD Acceptance Specifications. These figures exhibit a typical cross sectional view of 3 plated-through holes before after being subjected to thermal stress conditions. They indicate the LAMINATE EVALUATION AREA (Zone "B"), and the FOIL" and PLATING EVALUATION AREA (Zone "A"). Material, and plating quality characteristics shall be observed, and shall not exhibit the anomalies indicated in the following log:

POD QUALITY ASSURANCE INSPECTION LOG

X - SECTIONAL ANALYSIS

After Thermal Stress

LOT PRODUCTION REQUIREMENT CRACKING-INTERNAL FOIL/PLATE/COAT EVIDENCE-OUTGASSING LIFTED LANDS MEASLING IPC-600/3 SUBSURFACE IMPERFECT RESIN RECESSION FIG. 8 REQUIREMENTS LAMINATE VOIDS FIG 7&8 REQUIREMENTS THERMAL EVALUATION

USING THE POD ACCEPTANCE SPECIFICATIONS, CREATE AN OPERATOR INSPECTION LOG AND A QUALITY DATA BASE ON WHATEVER SOFTWARE PACKAGE YOU CHOOSE NOTE: CRK=INTERNAL CRACK, FOL=FOIL, PLT=PLATE, OUT=OUTGASSING, LFT=LIFTED LANDS, MES=MEASLING, SUB=SUBSURFACE IMPERFECTIONS, RES=RPODN RECESSION, LAM=LAMINATE VOIDS,

POD X-SECTION DATA BASE AFTER THERMAL STRESS CRK FOL PLT OUT LFT SUB RES LAM

The operator/inspector shall enter findings in the requirement column indicating lot production/job numbers based upon a production day. The operator/inspector shall then make examinations of specimens for the required inspection element, and shall make appropriate entries about measurements taken at this time.

Note: Anomalies determined to exceed required acceptance specifications, indicated in POD Specification Drawings 1 through 8, shall be reported immediately to the Quality Assurance Manager for proper disposition.

I've written, implemented, and used laboratory procedures for most all required test and analysis requirements for fab and assembly plus some others I forgot about.

Earl

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hey Steve

Who's brush roller conveyor is that?

Wayne

| Hey Ya' Chrys!! | | One other thing I can think of when it comes to looking at FAB vendors to rate how good they are, might be something that you may not be too concerned with (depending on the product you build), is their scoring capability. If you do a lot of panels, good scoring is important....there was a FAB vendor we quit doing business with when I was at Smart Modular because of the crappy score jobs we seemed to get all the time. Either the panels were scored too deep and fell apart before we finished building them, or it wasn't scored deep enough, setting us up for a bunch of fractured solder joints if we didn't catch the problem before depaneling. | | But, you may not need that capabilty...just thought I'd give you a little tip from experience. | | C-ya L8'ter! | | -Steve Gregory- |

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