You are correct about a TCE [CTE] mismatch issues in ceramic packages. The coefficient of thermal expansion [ppm/�C] of major ceramic package elements are: * Silicon - 3 * Standard 92% alumina ceramic � 6.5 * FR4 board � 18-20
Several points are: * Usually plastic BGA [PBGA] packages use soft, near eutectic solder balls. * Usually ceramic BGA [CBGA] packages use hard [10/90] solder balls. * Some ceramic packages use hard solder columns instead of balls. * Typically, ceramic array packages range in size from 18.5 to 32.5mm. 1.27mm pitch ball counts range from 196 to 625. 1.0mm pitch ball counts range from 292 to 937. * We have never seen a large BGA resistor array, not that that means much. Must ceramic resistor arrays that we see are LCCC. Search [maybe on: castel*, netwo*, etc] the fine SMTnet archives for further discussion. * Two JEDEC packages, TO-156 & TO-157, specify CBGA package body size and tolerances, ball array size, total number of balls, ball diameter, coplanarity of the array, and true position of the array.
Most of the work on ceramic array packaging comes out of IBM Microelectronics, maybe Poughkeepsie, NY. Marie S. Cole would know.
reply »