Comments [questions] are: * It�s strange that an uggie ol� SOIC, 50 pitch, BIG honkin� solder pad, kinda thang is failing. Sumpin aint kosher, yano? * Where is the failure occurring [ie, lead to pad, pad to board, etc]? Talk about the breadth and distribution of the problem. * We have found that the curing of potting can damage solder connections. What compound are you using? What is your cure recipe? * Your accelerated environmental testing is aggressive, regardless of the product end-use environment. Consider reviewing the need for cycling below 0�C. Understand why you�re not using a dwell of maybe 15 minutes, depending on the assembly [just enough time to get it to temperature]. You could increase your ramp to <20�C/min to compensate, somewhat, for the time lost to dwell. What is the product end-use environment? [Well, maybe the thinking on the �slow ramp / no dwell� was that with a slow ramp, the dwell wasn�t needed. Could be.] Finally, does this temperature measurement include the effect of voltage and current on the assembly? Or is this �box temperature�? * Sometimes cracking like this can be tracked back to board design. If this is limited is scope, talk about pad dimension, spacing, and shape. * How are sure the IPT (in process test) is capable of detecting the problem?
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