Investigation of Device Damage Due to Electrical Testing, R Croughwell & J McNeill, Worcester Polytechnic Institute Abstract: This paper examines the potential failure mechanisms that can damage modern low voltage CMOS devices and their relationship to electrical testing. Failure mechanisms such as electrostatic discharge (ESD), CMOS latch-up, and transistor gate oxide degradation can occur as a result of electrical over-voltage stress (EOS). In this paper, EOS due to electrical testing is examined and an experiment is conducted using pulsed voltage waveforms corresponding to conditions encountered during in-circuit electrical testing. Experimental results indicate a correlation between amplitude and duration of the pulse waveform and device degradation due to one or more of the failure mechanisms. [http://www.teradyne.com/atd/resource/docs/testStation/tpWPI.pdf ]
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