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No Clean OSP process cause ICT testing issue due to Flux building in testvia hole

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SMTA-Vikram

#82241

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole | 29 March, 2019

Hi guys, I am sure you all aware that since no clean OS process introduce, ICT test yield went down due to hi NDF. During No clean process, Flux is building in testvia hole that cause probes tip dirty and flux material stick on probe tip. Due to dirty Probe tip , it has poor contact on test points and will have NDF( no defect found) failures. We have tried different Paste and Flux, but we have >3% NDF. We using 8oz 90 degree blade type razor probes, still same issue. Is there stencil we can use or selective pasting test via so flux will not build in testvia.

any help or guidance will be appreciate.

This message was posted via the Electronics Forum @ SMTASMTA

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#82246

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole | 29 March, 2019

Why are you printing paste on test via? In the old days, we probed soldered pads to cushion impact force of probing. Is that still a reasonable practice?

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SMTA-Vikram

#82287

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole | 3 April, 2019

We still use Via as test points. so we need to paste Via. Pasting will make better contact with probes compare to test via without solder.

This message was posted via the Electronics Forum @ SMTASMTA

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#82295

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole | 4 April, 2019

That's what I guessed.

Some ideas to consider are:

Reduce usage of flux to the bare minimum.

Choose a low solids flux

Flux residues can be categorized as soft, brittle, sticky but this depends mostly on the formulation of the flux and the resins and the solvents used to make it. Flux residues will require specific probe designs and pin pressures to insure penetration and self=cleaning.

Change probe styles, materials and spring forces.

Develop a solid maintenance program to clean the probes

Clean your boards

Change your fixture design

Ask vendors [eg, Ingun, IDI, QATech, Everett Charles Technologies, etc] for advice.

Ask vendors [eg, Kester, Indium, Nihon, etc] for advice.

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#82296

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole | 4 April, 2019

Hi Vikram,

Have you looked at the rotating flux buster style pins? A few people do them, but this is probably the best illustration:

https://ingun.com/en/Products/ProductGroups/ICT_FCT/CategoryFolder/RotatingTestProbes

We also find that the longer we leave flying probe on No Clean boards, the more false calls we get as the residue appears to harden.

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SMTA-Vikram

#82341

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole | 11 April, 2019

Yes, we have try different Flux, probes. etc... also not to paste vs Paste Via, but still we have ~3% NDF due to contact issue.

I am looking for selective pasting with less flux dispenser.Any idea or anyone has used?

What about plug via before paste it.. what will be cost impact and how reliable will be.

This message was posted via the Electronics Forum @ SMTASMTA

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SMTA-Vikram

#82342

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole | 11 April, 2019

Thanks for info regarding rotating probe head. We do not recommending to use this probes as it may damage bare board as it will pierce thru board and will shorted etches..

Avoid using this probe for PWBA

This message was posted via the Electronics Forum @ SMTASMTA

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#82721

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole | 7 June, 2019

dont usually see this unless the Rosin hasnt been hardened due to low reflow or excessive pressure on blades squeezing flux out so you have flux rich areas. Are these boards also flow soldered?

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