PCB TOLERANCE - PANEL ARRAY VS SINGLE

Does class 2 vs class 3 PCBs effect variance/tolerance in terms of actual positioning of pads/traces? For example, if fiducial is to be at 10mm. What's the tolerance for class 2 vs class 3? [variance allowed]

Does panelization have any effect on this? Can errors accumulate across a panel, so for example if let's say tolerance was 0.05mm, if 5up panel had 0.05mm variance across each array, would that result in the farthest pcb being actually 0.05 x 5 difference?

Or is the tolerance the same across the entire panel, since from assembly stand point it's technically manufactured as one large pcb and only made into arrays at cutting? (as I assume coordinates even for arrays are just offset from origin, therefore array 12 is still technically based off array 1's origin therefore the tolerance would be panel based rather than array based?)

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