Need advise on regarding Vias

Hi All

I have a 0.7 mm diameter hole for vias, what�s the minimum annular ring for this hole diameter? Ans: Fur inner layers Min = .006" hole-pad annular ring ; inner pad dia - hole dia/2 For outer layers Min = .005" hole-pad annular ring ; outer pad dia - hole dia/2. For Inner & outer layers Min .008" clearanse to edges of drilled keyway slot.

If the designed annular ring is under the above mentioned min requirement then a "tear drop" may be added.

Designed annular ring is the difference between a pad & the corresponding drilled hole , divided by 2.In some cases due to drill wander the hole is tangent to the pad.So for these case manufactured annular ring will be = the thickness of the plated copper in the hole.

For more accuracy pls refer to your in hose PWB fab house capability.

Another thing is that our boards are coated with SMOBC solder mask, are the vias of the proto-type board considered tented?

Ans : Some are tented and some aren't.

Well it look's like you had a "industrial dispute" problem at your hand .Nothing more that I can say execept that if you had doubt after too much study of the "IPC Bibble" please refer to your PWB equipment capability and or fab criteria.

Good luck,

Regards.

reply »

Armin: How ya doin� bud? CK gives good advice, but I'd like to take a bit of a different angle.

Q1. For 0.7 mm (0.027in) diameter hole for vias, what�s the minimum annular ring for this hole diameter? Depends on what you�re trying to do. For instance:

Pad To Hole Ratio. For example, determine the pad size to produce a minimum annular ring and avoid breakout:

Drill size |0.018 inch Fabrication tolerance|0.012 inch (or whatever your supplier says) 2 times the min. annular ring |0.002 inch Pad size|0.032 inch

Taking a different angle, two points are: (1) Minimum via pad diameters vary according to substrate thickness. (2) The ability to use vias as test pads is part of the reason for selecting via pad size and separation.

So for 1.57 mm (0.062") thick boards, our minimum via diameter is: 0.33 mm (0.013") and the pad diameter is 1 mm (0.033"). We prefer 1 mm (0.040") pads.

Q2. What�s the term unsupported and supported holes refer to in IPC-2221 9.1.2 Annular Ring Requirements?

Supportive (Supported) Hole. A hole in a printed circuit board that has its inside surface plated or otherwise reinforced. Unsupported Hole. A hole containing no plating or other type of conductive reinforcement.

Q3. The separation gap between these holes from some of the pad edges of (some) the components were 0.25 mm (0.009 in) to 0.30 mm (0.012 in) only.

We like a 0.50 mm (0.02") separation. The minimum separation is 0.25 mm (0.01").

Q4. Some of these vias are located under SOIC�s and discretes.

Locating vias under any component is bad practice.

Q5. Boards are SMOBC solder mask, are the vias of the proto-type board considered tented?

SMOBC (Solder Mask Over Bare Copper). In printed circuit board fabrication, when the final metalization is copper with no other protective metal and non-soldereable areas are covered with a solder resist. This tells you nothing about the type of solder mask. Solder mask types have different capabilities to tent vias, ranging from: wet film tenting vias well to dry film tenting vias OK to LPI (Liquid Photo-Imageable) tenting vias poorly.

Q6. Is this the correct way of doing cost reduction?

It�s a good way of reducing the cost of fabricated boards, but that�s not the only cost your company writes check for. The "correct way" depends on the company, it�s goals for product development expediency and cost minimization, and a bunch of other stuff.

First, let�s separate the issues. Via hole size selection affects board fabrication cost. Via pad size has (virtually) no affect on board fabrication cost, but does affect testability and board reliability. Feature separation has (virtually) no affect on board fabrication cost, but does affect manufacturability and testability. Use of SMBOC affects both board fabrication and assembly cost. Solder mask type affects board fabrication and may affect assembly cost, depending on component pitch and manufacturing processes.

If your R&D people truly "know where" they�re "going," they (1) shouldn�t keep it a secret from the rest of the company and (2) should be able to explain to manufacturing process and quality types how these proposed changes reduce the shipped cost of the product, while improving reliability, and get their "buy-in" to the approach.

My2�

Dave F

reply »