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Castellated Solder Pads

Joseph Scott Dowsett


Castellated Solder Pads | 14 December, 2000

I am student at Northern Illinois University and am doing a senior design project on applying castellated solder pads (pads on the side of the substrate) to a hybrid circuit. I have had difficulty finding related articles. I found this website and thought I would give it a chance. If anyone has any ideas, please respond to

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Re: Castellated Solder Pads | 16 December, 2000

Castellation. A recessed metalized feature on the edge of a leadless chip carrier [LCC] that is used to interconnect conducting surface or planes within or on the chip carrier.

If you search the fine SMTnet Archives, you find: * A fine thread [castellations vs. no castellations - Jon Prokop 18:28:10 07/26/1999] from the fine SMTnet Archives by two fine old timers [Earl Moon & Steve Gregory] who are no longer participating in the fine SMTnet Forum. * A bonus throw-in [WAVE SOLDERING 0603 CHIP RESISTOR ARRAYS - Robert Hutton-Squire 11:56:35 04/10/2000] that talks to resistor networks with castellated terminals, although nothing in the thread would give you that idea, nor would there be any way you could find it, unless you were rattling on in the thread. * Few other threads � leading to question that has to be at nagging you. "What�s the deal with castellated solder pads [terminations]? There�s nothing on the net. There�s nothing on SMTnet. What am I missing?"

Consider the following IPC documents: * 2225 - Sectional Design Standard for Organic Multichip Modules (MCM-L) and MCM-L Assemblies * DD-135 - Qualification Testing for Deposited Organic Interlayer Dielectric Materials for Multichip Modules * 2220 - IPC 2220 Series * 2225 - Sectional Design Standard for Organic Multichip Modules (MCM-L) and MCM-L Assemblies * 6010-SERIES - IPC-6010 Series * 6015 - Qualification & Performance Specification for Organic Multichip Module (MCM-L) Mounting & Interconnect * JPCA-RDMAP98 - Report on Technology Roadmap for Advanced System Integration & Packaging

Consider talking to folk at RADC in Rome, NY [just down the road from you]

Consider talking to folk at failure analysis labs that specialize in electronics.You can find a list by searching the fine SMTnet Archives.

Now, I know you didn�t tell us about the package you plan to castellate, but this babbling may add something. [Well, at least I�ll be amused.] I think the big question is "Did the people who designed the LCC package think about how it might be attached?" Perhaps they only planned on using a socket. LCC packages have two problems: 1) How to solder attach the component 2) How to keep the solder joints from failing in fatigue.

Of the two the second is the larger problem unless your application is in a very benign and stable (non-cyclic) environment or your PCB is CTE-constrained (copper-Invar-copper P/G layers) to 9 ppm/C or less.

[There I got it out!!! We don't talk about them because we don't see them very much. We don't see them very much, because they sink. Sorry, maybe there's still time to do a project on the reliability of vias filled with conductive epoxy.]

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