Wafer-Level Packaging Symposium

Wafer-Level Packaging Symposium

Advanced Packaging: The Dawn of a New Era

The Wafer-Level Packaging Symposium will bring together the semiconductor industry’s most respected authorities to address all aspects of wafer-level, 3D device packaging, advanced manufacturing & test technologies.

Addressing wafer-level packaging, 3D, and Advanced Manufacturing & Test technologies, the Wafer-Level Packaging Symposium will be at the forefront of packaging technology evolution. The conference will feature attendees from over 16 countries in the heart of Silicon Valley to immerse themselves in the latest technology and business trends.

The technical program and exhibition focus on semiconductor packaging and advanced wafer-level packaging technology featuring 3 tracks in Wafer-Level Packaging, 3D Integration, and Advanced Manufacturing and Test.

Submission Deadline: Friday, September 10, 2021

https://smta.org/wafer

When:February 15-17, 2022
8:00 AM

Where:DoubleTree by Hilton Hotel San Jose
2050 Gateway Place
San Jose, California  95110
United States

Contact:SMTA Headquarters
waferlevel@smta.org
952-920-7682

Advanced Packaging: The Dawn of a New Era

The development of Advanced Package Technology is undergoing a massive change because Electrical System Architects are directly driving package performance requirements, something which has never happened before. Previously System Architects designed circuits around package limitations because pushing package technologies outside of their “comfort zones” often led to undesirable results.

With the rise in transistor costs and the need to improve power efficiency, Silicon Architects have little choice but to push advanced package technologies well beyond their comfort zones