Wafer-Level Packaging Symposium

Wafer-Level Packaging Symposium

When: February 14-16, 2024  - 8:00 AM

Where: Hyatt Regency San Francisco Airport
1333 Bayshore Highway
Burlingame, California  94010
United States

Contact:SMTA Headquarters
wafer@smta.org
(952) 920-7682

Formatting Advanced Packaging for the AI Era

 The development of Advanced Package Technology is undergoing a massive change because Electrical System Architects are directly driving package performance requirements, something which has never happened before. Previously System Architects designed circuits around package limitations because pushing package technologies outside of their “comfort zones” often led to undesirable results.

With the rise in transistor costs and the need to improve power efficiency, Silicon Architects have little choice but to push advanced package technologies well beyond their comfort zones.

The Wafer-Level Packaging Symposium will bring together the semiconductor industry’s most respected authorities to address all aspects of wafer-level, 3D device packaging, advanced manufacturing & test technologies. Addressing wafer-level packaging, 3D, and Advanced Manufacturing & Test technologies, the Wafer-Level Packaging Symposium will be at the forefront of packaging technology evolution. The conference will feature attendees from around the globe in the heart of Silicon Valley to immerse themselves in the latest technology and business trends.