D68000 - 32-bit CISC Microprocessor Core

D68000 - 32-bit CISC Microprocessor Core Description:

Overview

• higher performance than standard 68000

• delivered with fully automated test-bench

• complete set of tests

The D68000 soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor. It has a 16-bit data bus and a 24-bit address data bus. Of course, its code is compatible with the MC68008, upward code compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. Our efficient IP Core has improved instructions set, which allows to execute a program with higher performance, than standard 68000 core.

The D68000 is delivered with fully automated test-bench and complete set of tests, which allow easy package validation, at each stage of SoC design flow. A special testing platform has been built to run D68000 with uCLinux Operating System. For more details, please check this link.

Features

■ Software compatible with industry standard 68000
■ MULS, MULU take 28 clock periods
■ DIVS, DIVU take 28 clock periods
■ Optimized shifts and rotations
■ Idle cycles removed to improve performance
■ Shorter effective address calculation time
■ Bus cycle timings identical to 68000
■ 32 bit data and address registers
■ 14 addressing modes:
■  Direct: Data register direct, Address register direct
■  Indirect: Register indirect, Postincrement register indirect, Predecrement register indirect, Register indirect with offset, Indexed register indirect with offset
■ PC relative: Relative with offset, Relative with index and offset
■ Absolute data: Absolute short, Absolute long
■ Immediate data: Immediate, Quick immediate
■ Implied

Benefits

■ Getting a sillicon proven IP tested with uCLinux
■ Rapid prototyping and time-to-market reduction
■ Design risk elimination
■ Development costs reduction
■ Full customization
■ Wide range of peripherals
■ Technological independence (VHDL and Verilog)
■ Global sales network
■ Professional service

Deliverables

■ Source code:
■ VHDL Source Code or/and
■ VERILOG Source Code or/and
■ Encrypted, or plain text EDIF netlist
■ VHDL & VERILOG test bench environment
■ Active-HDL automatic simulation macros
■ ModelSim automatic simulation macros
■ Tests with reference responses
■ Technical documentation
■ Installation notes
■ HDL core specification
■ Datasheet
■ Synthesis scripts
■ Example application
■ Technical support
■ IP Core implementation support
■ 3 months maintenance
■ Delivery the IP Core updates, minor and major versions changes
■ Delivery the documentation updates
■ Phone & email support

Tech Specs

FPGA - ALTERA APEX20KE; XILINX VIRTEX-E

Type - Soft Firm  

Equivalent Part - MC68000

Availability - Now

FPGA Technology:

Altera: Stratix II, Stratix GX, Stratix, HardCopy, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Spartan-3,
Actel: SX-A, ProASICPLUS, Axcelerator,