D16750 - Configurable UART with FIFO

D16750 - Configurable UART with FIFO Description:

Overview

The D16750 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C750. The D16750 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 64 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16750 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16750 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The D16750 has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.
The separate BAUD CLK line allow to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.
The configuration capability allows user to enable or disable during Synthesis process the Modem Control Logic and FIFO's Control Logic, change the FIFO size. So in applications with area limitation and where the UART works only in 16450 mode, disabling Modem Control and FIFO's allow to save about 50% of logic resources.
The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface D16750 core implementation and verification are very simply, by eliminating a number of clock trees in complete system.

Features

■ Software compatible with 16450, 16550 and 16750 UARTs
■ Configuration capability
■ Separate configurable BAUD clock line
■ Two modes of operation: UART mode and FIFO mode
■ Majority Voting Logic
■ In the FIFO mode transmitter and receiver are each buffered with 16 byte or 64 byte FIFO to reduce the number of interrupts presented to the CPU
■ Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
■ In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
■ Independently controlled transmit, receive, line status, and data set interrupts
■ False start bit detection
■ 16 bit programmable baud generator
■ MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
■ Fully programmable serial-interface characteristics:
■ 5-, 6-, 7-, or 8-bit characters
■ Even, odd, or no-parity bit generation and detection
■ 1-, 1½-, or 2-stop bit generation
■ Baud generation
■ Complete status reporting capabilities
■ Line break generation and detection. Internal diagnostic capabilities:
■ Loop-back controls for communications link fault isolation
■ Break, parity, overrun, framing error simulation
■ CTS and RTS hardware flow control
■ Technology independent HDL Source Code
■ Full prioritized interrupt system controls
■ Fully synthesizable static design with no internal tri-state buffers

Benefits

■ Rapid prototyping and time-to-market reduction
■ Design risk elimination
■ Development costs reduction
■ Full customization
■ Global sales network
■ Technology independence
■ Professional service
■ Getting a sillicon proven IP

Deliverables

■ Source code:
■ VHDL Source Code or/and
■ VERILOG Source Code or/and
■ Encrypted, or plain text EDIF netlist
■ VHDL & VERILOG test bench environment
■ Active-HDL automatic simulation macros
■ ModelSim automatic simulation macros
■ Tests with reference responses
■ Technical documentation
■ Installation notes
■ HDL core specification
■ Datasheet
■ Synthesis scripts
■ Example application
■ Technical support
■ IP Core implementation support
■ 3 months maintenance
■ Delivery the IP Core updates, minor and major versions changes
■ Delivery the documentation updates
■ Phone & email support

Tech Specs

Type - Soft  

Equivalent Part - TL16C750

FPGA Technology:

Altera: Stratix II, Stratix GX, Stratix, HardCopy, FLEX 10K, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Spartan-3,
Actel: SX-A, ProASICPLUS, Axcelerator,