Triconex 3008 Processor Module

Triconex 3008 Processor Module Description:

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XIAMEN YUEHANG COMPUTER ENGINEERING CO.LTD. is a company that professionally engaged in large system DCS spare parts supply. We supply DCS, PLC, MOTOROLA MVME, Anybus, RTU, IPC, IPC, SCSI (50, 68, 80Pin), AnyBus (Gateway) is a high-tech enterprise specialized in professional sales of industrial automation components, and is committed to improving the level of world automation parts supply.

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Company products cover DCS control system card, programmable PLC module SPS / CNC panel controller / inverter / server driver and various parts of the robot.

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Triconex 3008 Processor Module

Triconex 3008 Processor Module

Triconex 3008 Processor Module

Main Processor Modules Model 3008 Main Processors (MP) are available for Tricon v9.6 and later systems. For detailed specifications, see the Planning and Installation Guide for Tricon Systems.Three MPs must be installed in the Main Chassis of every Tricon system. Each MP independently communicates with its I/O subsystem and executes the user-written control program. 

Sequence of Events (SOE) and Time Synchronization During each scan, the MPs inspect designated discrete variables for state changes known as events. When an event occurs, the MPs save the current variable state and time stamp in the buffer of an SOE block.

If multiple Tricon systems are connected by means of NCMs, the time synchronization capability ensures a consistent time base for effective SOE time-stamping. See page 72 for more information. Diagnostics Extensive diagnostics validate the health of each MP, I/O module and communication channel. Transient faults are recorded and masked by the hardware majority-voting circuit. Persistent faults are diagnosed and the errant module is hot-replaced. MP diagnostics perform these tasks: • Verify fixed-program memory and static RAM

• Test all basic processor and floatingpoint instructions and operating modes • Validate user memory by means of the TriBus hardware-voting circuitry • Verify the shared memory interface with each I/O communication processor and channel • Verify handshake and interrupt signals between the CPU, each I/O communication processor and channel • Check each I/O communication processor and channel microprocessor, ROM, shared memory access and loopback of RS- 485 transceivers • Verify the TriClock and TriBus interfaces

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