A.T.E. Solutions, Inc.

The leading Test, ATE and Testability consulting and educational firm, offering various test related courses. Maintains the BestTest Directory, a test community knowledge base. Publishes The BestTest eNewsletter.

Consultant / Service Provider, Manufacturer, Training Provider

A.T.E. Solutions, Inc. is the one stop solution for your test, ATE and testability problems. Through its renoun test-related courses, publications and test community web site, the company collects and disseminates test knowledge. For more specific problems, expert consultants can provide consulting services in various aspects of test, including, Test Requirements Analysis, Test Strategy and Management, Building an ATE, Design for Testability Analysis and Recommendations, Built-In Self Test, Failure Mode and Effects Analysis, and many other test-related consulting. The company also develops and teaches courses for test vendors. A.T.E. Solutions, Inc., through its wide network in the industry can assist you with test programming, test services and production testing.

A.T.E. Solutions, Inc. Postings

3 products »


A.T.E. Solutions, Inc. is a world leader in electronics test consulting. We consult directly in many facets of test planning and testability topics. We have been providing solutions for test problems to both commercial and military clients for more t...

Test Services


The Testability Director

The Testability Director is a spreadsheet template, which guides in the development of testable designs. It contains the Inherent Testability Checklist used with MIL-STD-2165, the U.S. Government's Testability Program for Electronic Systems and Equip...

The Testability Director

Test Related Courses

Test, ATE and Design for Testability Courses and Educational Resources A.T.E. Solutions, Inc. is the world's leading education firm in the field of test technology. We offer a great variety of courses and educational resources in a number of s...

Test Related Courses

3 technical articles »

Creating Reusable Manufacturing Tests for High-Speed I/O with Synthetic Instruments

Jul 08, 2020 | Louis Y. Ungar, Neil G. Jacobson, T.M. Mak

There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort....

Design for Testability (DFT) to Overcome Functional Board Test Complexities in Manufacturing Test

Jun 20, 2018 | Louis Y. Ungar

Manufacturers test to ensure that the product is built correctly. Shorts, opens, wrong or incorrectly inserted components, even catastrophically faulty components need to be flagged, found and repaired. When all such faults are removed, however, functional faults may still exist at normal operating speed, or even at lower speeds. Functional board test (FBT) is still required, a process that still relies on test engineers’ understanding of circuit functionality and manually developed test procedures. While functional automatic test equipment (ATE) has been reduced considerably in price, FBT test costs have not been arrested. In fact, FBT is a huge undertaking that can take several weeks or months of test engineering development, unacceptably stretching time to market. The alternative, of selling products that have not undergone comprehensive FBT is equally, if not more, intolerable....

Causes and Costs of No Fault Found Events

Apr 14, 2016 | Louis Y. Ungar

A system level test, usually built-in test (BIT), determines that one or more subsystems are faulty. These subsystems sent to the depot or factory repair facility, called units under test (UUTs) often pass that test, an event we call No-Fault-Found (NFF). With more-and more electronics monitored by BIT, it is more likely that an intermittent glitch will trigger a call for a maintenance action resulting in NFF. NFFs are often confused with false alarm (FA), cannot duplicate (CNDs)or retest OK (RTOK) events. NFFs at the depot are caused by FAs, CNDs, RTOKs as well as a number of other complications. Attempting to repair NFF scan waste precious resources, compromise confidence in the product, create customer dissatisfaction, and the repair quality remains a mystery. The problem is compounded by previous work showing that most failure indications calling for repair action at the system level are invalid. NFFs can be caused by real failures or may be a result of system level false alarms. Understanding the cause of the problem may help us distinguish between units under test (UUTs) that we can repair and those that we cannot. In calculating the true cost of repair we must account for wasted effort in attempting to repair unrepairable UUTs.

This paper will shed some light on this trade-off. Finally, we will explore approaches for dealing with the NFF issue in a cost effective manner....

3 news releases »

Test Economics Course in Silicon Valley

Jan 07, 2010 | A 1-day Intensive Seminar on March 11, 2010

New Testability Group To Bring DFT to Management

Dec 05, 2007 | December 10, 2007 at 9 AM in San Jose

Cost Effective Test Covered in One Day Course

Mar 09, 2007 | ATE, DfT and BIST combined with Test Economics

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