SMT Equipment

DSPI - Serial Peripheral Interface Master/Slave

Category:

Other

Offered by:

Digital Core Design

Company Information:

Digital Core Design

DCD is a leading IP Core provider and SoC design house. The company was founded in 1999 and since the early beginning is considered as an expert in IP Cores architecture improvements.

Bytom, Poland

Service Provider

  • Phone +48 32 282 82 66

Digital Core Design website

Company Postings:

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DSPI - Serial Peripheral Interface Master/Slave Description:

Overview

The DSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI data are simultaneously transmitted and received. The DSPI is a technology independent design that can be implemented in a variety of process technologies. The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of eight different bit rates for the serial clock.
The DSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O), and address SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A writecollision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers if more than one SPI devices simultaneously attempts to become bus master.
DSPI is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
DSPI is a technology independent design that can be implemented in a variety of process technologies.

Features


■ SPI Master
■ Master and Multi-master operations
■ 8 SPI slave select lines
■ System error detection
■ Mode fault error
■ Write collision error
■ Interrupt generation
■ Supports speeds up 1/4 of system clock
■ Bit rates generated 1/4 - 1/512 of system clock.
■ Four transfer formats supported
■ Simple interface allows easy connection to microcontrollers
■ SPI Slave
■ Slave operation
■ System error detection
■ Interrupt generation
■ Supports speeds up 1/4 of system clock
■ Simple interface allows easy connection to microcontrollers
■ Four transfer formats supported
■ Fully synthesizable
■ Static synchronous design
■ Positive edge clocking and no internal tri-states
■ Scan test ready


Tech Specs

Type - Soft Firm  

Availability - Now

FPGA Technology:

Altera: Stratix, FLEX 10K, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Spartan-3,
Actel: SX-A, ProASICPLUS, Axcelerator,

DSPI - Serial Peripheral Interface Master/Slave was added in Apr 2012

DSPI - Serial Peripheral Interface Master/Slave has been viewed 336 times

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