Jet Propulsion Laboratory

The JPL is the lead U.S. center for robotic exploration of the solar system, and conducts major programs in space-based Earth sciences and astronomy.

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Jet Propulsion Laboratory (JPL) is a federally funded research and development center and NASA field center located in Pasadena, California.

JPL is managed by the nearby California Institute of Technology (Caltech) for the National Aeronautics and Space Administration. The Laboratory's primary function is the construction and operation of robotic planetary spacecraft, though it also conducts Earth-orbit and astronomy missions. It is also responsible for operating NASA's Deep Space Network.

Among the Laboratory's current major active projects are the Mars Science Laboratory mission (which includes the Curiosity rover), the Cassini - Huygens mission orbiting Saturn, the Mars Exploration Rovers (Spirit and Opportunity), the Mars Reconnaissance Orbiter, the Dawn mission to the dwarf planet Ceres and asteroid Vesta, the Juno spacecraft en route to Jupiter, the Gravity Recovery and Interior Laboratory (GRAIL) mission to the Moon, the Nuclear Spectroscopic Telescope Array (NuSTAR) X-ray telescope, and the Spitzer Space Telescope.

Jet Propulsion Laboratory Postings

4 technical articles »

Assembly Reliability of TSOP/DFN PoP Stack Package

Dec 12, 2018 | Reza Ghaffarian, Ph.D.

Numerous 3D stack packaging technologies have been implemented by industry for use in microelectronics memory applications. This paper presents a reliability evaluation of a particular package-on-package (PoP) that offers a reduction in overall PCB board area requirements while allowing for increases in functionality. It utilizes standard, readily available device packaging methods in which high-density packaging is achieved by: (1) using standard "packaged" memory devices, (2) using standard 3-dimensional (3-D) interconnect assembly. The stacking approach provides a high level of functional integration in well-established and already functionally tested packages. The stack packages are built from TSOP packages with 48 leads, stacked either 2-high or 4-high, and integrated into a single dual-flat-no-lead (DFN) package....

Defect Features Detected by Acoustic Emission for Flip-Chip CGA/FCBGA/PBGA/FPBGA Packages and Assemblies

Jun 22, 2017 | Reza Ghaffarian, Ph.D.

C-mode scanning acoustic microscopy (C-SAM) is a non-destructive inspection technique showing the internal features of a specimen by ultrasound. The C-SAM is the preferred method for finding “air gaps” such as delamination, cracks, voids, and porosity. This paper presents evaluations performed on various advanced packages/assemblies especially flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. For comparison, representative x-ray images of the assemblies were also gathered to show key defect detection features of the two non-destructive techniques....

Thermal Shock and Drop Test Performance of Lead-free Assemblies with No-Underfill and Corner-Underfill

Jan 02, 2014 | Bankeem Chheda and S. Manian Ramkumar, Ph.D.; Rochester Institute of Technology-CEMA, Reza Ghaffarian; Ph.D. Jet Propulsion Laboratory.

With ROHS compliance the transition to lead-free is inevitable. Several lead-free alloys are available in the market and its reliability has been the main concern. The results from this experimental research aims at making a comparison of different lead-free alloy combinations. Thermal shock and drop tests are a part of this experimental study....

Assembly and Reliability of 1704 I/O FCBGA and FPBGAs

Mar 14, 2013 | Reza Ghaffarian, Ph.D.

Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings....

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