NASA Office Of Safety And Mission Assurance

The Office of Safety and Mission Assurance (OSMA) assures the safety and enhances the success of all NASA activities through the development, implementation and oversight of agencywide safety, reliability, maintainability and ...

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8 technical articles »

Microelectronics Reliability: Physics-of-Failure Based Modeling and Lifetime Evaluation

Apr 22, 2024 | Mark White and Joseph B. Bernstein

The solid-state electronics industry faces relentless pressure to improve performance, increase functionality, decrease costs, and reduce design and development time. As a result, device feature sizes are now in the nanometer scale range and design life cycles have decreased to fewer than five years. Until recently, semiconductor device lifetimes could be measured in decades, which was essentially infinite with respect to their required service lives. It was, therefore, not critical to quantify the device lifetimes exactly, or even to understand them completely. For avionics, medical, military, and even telecommunications applications, it was reasonable to assume that all devices would have constant and relatively low failure rates throughout the life of the system; this assumption was built into the design, as well as reliability and safety analysis processes....

Body of Knowledge (BOK) for Leadless Quad Flat No-Lead/Bottom Termination Components (QFN/BTC) Package Trends and Reliability

Sep 18, 2023 | Reza Ghaffarian, Ph.D.

As with many advancements in the electronics industry, consumer electronics is driving the trends for electronic packaging technologies toward reducing size and increasing functionality. Microelectronics meeting the technology needs for higher performance, reduced power consumption and size, and off the- shelf availability. Due to the breadth of work being performed in the area of microelectronics packaging/components, this report limits it presentation to board design, manufacturing, and processing parameters on assembly reliability for leadless (e.g., quad flat no-lead (QFN) or a generic term of bottom termination component (BTC)) packages. This style of package was selected for investigation because of its significant growth, lower cost, and improved functionality, especially for use in an RF application....

HALT/HASS and Thermal Cycling to Assess COTS Boards, GoPro Camera and Advanced PBGA/CCGA Virtex-5Electronic Packages

Aug 14, 2023 | Rajeshuni Ramesham Ph.D.

Outline Introduction Objectives Hardware to be assessed COTS Xilinx and Microsemi ProASIC Boards Advanced CCGA/Virtex-5Daisy Chain Package (Kyocera) Assembled Advanced SMT packages (PBGA) COTS GoPro Camera Experimental Details Test Results/Discussion Summary Acknowledgements...

PCB Quality Metrics that Drive Reliability

Jan 23, 2023 | Bhanu Sood, Ph.D.

PDC Outline Section 0: Intro Section 1: What is reliability and root cause? Section 2: Overview of failure mechanisms Section 3: Failure analysis techniques – Non-destructive analysis techniques – Destructive analysis – Materials characterization Section 4: Summary and closure...

Cracking Problems in Low-Voltage Chip Ceramic Capacitors

Sep 25, 2022 | Alexander Teverovsky

Cracking remains the major reason of failures in multilayer ceramic capacitors (MLCCs) used in space electronics. Due to a tight quality control of space-grade components, the probability that as manufactured capacitors have cracks is relatively low, and cracking is often occurs during assembly, handling and the following testing of the systems. Majority of capacitors with cracks are revealed during the integration and testing period, but although extremely rarely, defective parts remain undetected and result in failures during the mission. Manual soldering and rework that are often used during low volume production of circuit boards for space aggravate this situation. Although failures of MLCCs are often attributed to the post-manufacturing stresses, in many cases they are due to a combination of certain deviations in the manufacturing processes that result in hidden defects in the parts and excessive stresses during assembly and use. This report gives an overview of design, manufacturing and testing processes of MLCCs focusing on elements related to cracking problems. The existing and new screening and qualification procedures and techniques are briefly described and assessed by their effectiveness in revealing cracks. The capability of different test methods to simulate stresses resulting in cracking, mechanisms of failures in capacitors with cracks, and possible methods of selecting capacitors the most robust to manual soldering stresses are discussed....

Reliability of PWB Microvias for High Density Package Assembly

Dec 21, 2021 | Reza Ghaffarian, Ph.D.

High density PWB (printed wiring board) with microvia technology is required for implementation of high density and high I/O area array packages (AAP). COTS (commercial off-the-shelf) AAP packaging technologies in high reliability versions with 1.27 mm pitch are now being considered for use in a number of NASA systems including the Space Shuttle and Mars Rovers. NASA functional system designs are requiring ever more denser AAP packages and board features, making board microvia technology very attractive for effectively routing a large number of package inputs/outputs....

Printed Circuit Board Quality: Copper Wrap

Jul 20, 2021 | Jeannette Plante, BhanuSood, Kelly Daniluk

Motivation: High reject rates for PCBs due to specification non-conformances Multiple rebuilds causing impactful schedule delays + Copper Wrap + Wicking + Etchback + Annular Ring Are rejected boards reliable? What are PCB quality requirements for? + Reliability: fewer cycles-to-failure? + Manufacturability: define threshold of modern manufacturing capability?...

A Study on Effects of Copper Wrap Specifications on Printed Circuit Board Reliability

Jul 20, 2021 | Bhanu Sood, John Shue, Jesse Leitner, Kelly Daniluk, Lionel-Nobel Sindjui

During the manufacturing of printed circuit boards (PCBs) for a Flight Project, it was found that a European manufacturer was building its boards to a European standard that had no requirement for copper wrap on the vias. The amount of copper wrap that was measured on coupons from the panel containing the boards of interest was less than the amount specified in IPC-6012 Rev B, Class 3. To help determine the reliability and usability of the boards, three sets of tests and a simulation were run. The test results, along with results of simulation and destructive physical analysis, are presented in this paper. The first experiment involved subjecting coupons from the panels supplied by the European manufacturer to thermal cycling. After 17 000 cycles, the test was stopped with no failures. A second set of accelerated tests involved comparing the thermal fatigue life of test samples made from FR4 and polyimide with varying amounts of copper wrap. Again, the testing did not reveal any failures. The third test involved using interconnect stress test coupons with through-hole vias and blind vias that were subjected to elevated temperatures to accelerate fatigue failures. While there were failures, as expected, the failures were at barrel cracks. In addition to the experiments, this paper also discusses the results of finite-element analysis using simulation software that was used to model plated-through holes under thermal stress using a steady-state analysis, also showing the main failure mode was barrel cracking. The tests show that although copper wrap was sought as a better alternative to butt joints between barrel plating and copper foil layers, manufacturability remains challenging and attempts to meet the requirements often result in features that reduce the reliability of the boards. Experimental and simulation work discussed in this paper indicate that the standard requirements for copper wrap are not contributing to the overall board reliability, although it should be added that a design with a butt joint is going to be a higher risk than a reduced copper wrap design. The study further shows that procurement requirements for wrap plating thickness from Class 3 to Class 2 would pose little risk to reliability (minimum 5 μm/0.197 mil for all via types).Experimental results corroborated by modeling indicate that the stress maxima are internal to the barrels rather than at the wrap location. In fact, the existence of Cu wrap was determined to have no appreciable effect on reliability....

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