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Drop Impact Reliability of Edge-bonded Lead-free Chipscale Packages

Drop Impact Reliability of Edge-bonded Lead-free Chipscale Packages

CSP I/O traces and component orientationThis paper presents the drop test reliability results for edge-bonded 0.5mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board.

The test boards were subjected to drop tests at several impact pulses (...) Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding.

Authors:

Andrew Farris, Jianbiao Pan, Albert Liddicoat, Michael Krist, Nicholas Vickers, Brian J.Toleno, Dan Maslyk, Dongkai Shangguan, Jasbir Bath, Dennis Willie, David A. Geiger.

Company / Organization:

Cal Poly State University, Henkel Corporation, Flextronics International

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Forum

AOI side camera | Posted by mark slade

I have a mirtec MV-3L, does any one know, when drawing a component part with varios side angle camera views can i group that part and its camera views to save in the library and if so how?... »»

SAC BGA in Pb Process | Posted by CL

We have successfully avoided (for the most part) the mixed alloy situation since the introducion of the RoHS directive. We are now seeing an influx of RoHS BGA components on leaded assemblies... »»

Solder void underneath the mosfet | Posted by Sean

Anyone used to come across solder void underneath mosfet as shown in the attached file? Will this pose any reliability issue, such as get burnt during functional test?... »»

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SMTnet Express
March 31, 2010

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