Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections, on the other hand, has proved to be more efficient and, even though two interposers are required, more economical. The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern.
This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface technology...
Koloa, Hawaii, USA | February 2 | SMTA - a premier forum for networking among microelectronics professionals and business leaders throughout the world...
SMTA - Surface Mount Technology Association is a non-profit international association of companies and individuals (totalling 4,000) involved in all aspects of advanced electronics assembly, surface mount and related technologies.
IPC - Association Connecting Electronics Industries is a US-based trade association dedicated to the competitive excellence and financial success of its nearly 2,600 member companies which represent all facets of the electronic interconnection industry, including design, printed wiring board manufacturing and electronics assembly.
