Electronics Forum | Mon May 10 15:26:11 EDT 2004 | hertenstein
Sorry, I was not clear. I am interested in the strain on the PCB during depanelization using a parallel blade shear. And the effect on ceramic capacitors on the PCB. I was not shearing the capacitor off of the PCB. Regards, Jeff
Electronics Forum | Mon May 10 14:40:14 EDT 2004 | hertenstein
I am looking for a industry specification for the amount of strain that is allowable during a parallel blade shearing operation as related to ceramic capacitors. Does anyone know of such a specification? Best regards, Jeff
Electronics Forum | Mon May 10 17:33:13 EDT 2004 | davef
Oh, OK. There is not specification for that either. Capacitor fabricators [eg, TDK, Kemet, AVX, etc] give good guidelines. For instance: http://www.kemet.com/kemet/web/homepage/kechome.nsf/vapubfiles/F2111/$file/F2111.pdf
Electronics Forum | Tue Jun 29 14:55:22 EDT 2010 | rgduval
For the capacitors that Yageo analyzed... Were they taken out at representative points in the process?? ie. were samples taken from pre-assembly, pre-ICT, post-conformal coat, post-final test? You note that the parts 'seem' to be ok up to ICT. And
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