Electronics Forum | Wed Mar 21 16:32:03 EST 2001 | mparker
The root cause is dependant on the type of solder "splash", ball, whatever, that you are seeing post reflow. If it is smears, then cleaning the stencil underside is probably the answer. Are you using automatic wipers? How many print cycles between w
Electronics Forum | Wed Feb 14 08:15:08 EST 2007 | CK the Flip
I agree with Rob that voids are often times paste-dependent, and it's all about the type of flux that's used. The cause of the voids, as you all know, is outgassing of flux which has nowhere to go with BGA's. Some paste mfgrs. will recommend going
Electronics Forum | Thu Jun 22 15:05:55 EDT 2017 | solderingpro
There are several different technologies in the industry today to assist in the out-gassing of flux cores. On automated soldering systems, there are two main types of perforating solder feeders: - Hole Drilling - "V" Scoring By perforating the so
Electronics Forum | Fri May 31 18:00:55 EDT 2013 | hegemon
With regards to first picture.(Large themal vias) I would attempt to measure the area of the ground pad, less the area of the "drain" holes or Thermal Vias. From that result I would reduce the aperture to account for about 50% coverage of that remai
Electronics Forum | Sun Mar 25 08:45:00 EDT 2018 | jacobidiego
Normally some random components of size 0604 or below and may be due to a thermal mass being close like a transformer or AC electrolytic caps. We tried changing fan speed, but this will change the thermal profile and avoid the thermal mass from bein
Electronics Forum | Wed Oct 04 14:18:05 EDT 2006 | C.K. the Flip
The main cause of voids is your flux out-gassing during reflow. Try a little "knee" or slight soak in your thermal profile to dry out the volatiles a bit. Typical soak ranges from 130 deg. C to 170 deg. C for around 30-90 seconds.
Electronics Forum | Thu May 19 13:03:18 EDT 2005 | russ
On the non-wetted holes put a solder iron to them and see if they "bubble" if so, you have some outgassing in your PCB and they will need to be baked prior to assembly. If this is okay I would investigate the grnd layer that was mentioned. What is
Electronics Forum | Wed Jun 05 12:22:45 EDT 2002 | Bob
No. Placement force is fine. Also boards have been inspected prior to reflow using microscope with no evidance of misplaced solder balls. The ramp rate has been reduced to acceptable limits, typically .8 - 1.5 degrees per sec. Outgassing from eithe
Electronics Forum | Fri Jun 20 18:32:55 EDT 2008 | hegemon
Back when I used to do a lot of these style devices we ran into the same problem you are describing. Use a pattern for the center pad area and keep the total coverage to about 68% of the pad area. Diagonal Stripes, tic tac toe, cloverleaf, dot array
Electronics Forum | Tue Aug 06 17:43:10 EDT 2013 | davef
I agree with SOB. First, someone is thinking too much and has too much idle time. And second, controlling volatiles from routine fluxing should be much more concerning than volatiles from out-gassing from delamination. In most plants, delamination is
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