Electronics Forum: via hole wall copper thickness (Page 1 of 4)

SMD Via hole design-thermal performance

Electronics Forum | Thu Oct 30 23:39:10 EDT 2014 | beilimanu

No paper thing, while I can make some suggestions based on my experience. what is the size of your via? If it's smaller than dia0.4mm, in PCB production process it should be filled by soldermask. So my suggestion is design it to be full filled by SM

Solder in via holes causing printing problems

Electronics Forum | Thu Jan 06 06:15:49 EST 2005 | mattkehoe

We need some opinions about a situation that is causing problems in our process. The pcb's in question are .125 thick with a HASL finish. The boards are coming in with a large amount of solder trapped inside the via holes. Sometimes this solder is ac

PCB Delamination in PTH hole

Electronics Forum | Tue Oct 27 16:22:00 EDT 2009 | davef

It's not the first thing we think of in looking at your picture. First off, the lack of copper in the region of the red oval makes us think of a plating defect. We don't expect that moisture out-gassing through the barrel wall to show-up on opposite

Paste in hole (sate of the art)

Electronics Forum | Tue Feb 21 11:59:56 EST 2006 | dannyleach

We design a broad range of DC/DC power supplies for various telecom, internet, and computor applications and have been succesfully using intrusive reflow for ~7 years now. Our pcbs range from 0.065 to 0.090 in thickness and are moslty dense 4 to 8 la

Re: PCB Standards

Electronics Forum | Wed Jun 10 18:40:00 EDT 1998 | Earl Moon

| I am looking for the Industry standards on vias. Are they required to be plated with solder or is copper plating enough? What about reliabilty with either one? Also, if tenting the via is required should it be copper plated or solder plated over

Re: Plating crack

Electronics Forum | Wed Sep 27 19:37:32 EDT 2000 | Dave F

Wolfgang is correct. Copper plating thickness of the via barrel walls is a key question you need to answer to troubleshoot this. Tenting is a red herring.

Re: Assembly of CSP on pads with vias.

Electronics Forum | Sat Jan 23 13:29:40 EST 1999 | Earl Moon

| Hi Everyone, | We plan to build, for reliability/experimental/research purpose some CSPs (namely Tessera microBGA 46-I/O 0/75mm pitch and TI 64 I/O 0/8 mm pitch). the various factors that we plan to evaluate are the reliability and assembly concern

Baking populated PCBs

Electronics Forum | Wed Sep 09 08:25:40 EDT 2009 | davef

We understand that you have boards in production that you need to ship. In the future, you could eliminate your moisture caused blow hole issue a lot more simply than baking. Consider requiring that your board fab plate the copper thickness of throug

Re: Via's in BGA pads

Electronics Forum | Wed Apr 21 17:11:05 EDT 1999 | Earl Moon

| Does anyone have any experience with soldering 50mil pitch BGA's that have a via in the pad, the size is .012 The via will be masked off on the bottom side of the board. Need to know what precautions or problems if any I might encounter. The proces

Re: Via's in BGA pads

Electronics Forum | Wed Apr 21 19:09:10 EDT 1999 | Earl Moon

| | Does anyone have any experience with soldering 50mil pitch BGA's that have a via in the pad, the size is .012 The via will be masked off on the bottom side of the board. Need to know what precautions or problems if any I might encounter. The proc

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