Technical Library | 2015-08-27 15:32:16.0
Ever since there has been a widespread usage of surface mount parts, the trend of continued shrinkage of devices with ever finer pitches has continued to challenge PCB assemblers for the rework of same. Todays' pitches are commonly 0.5 to 0.4mm with packages of tiny outline sizes, 5 -10mm square, making the rework of such devices a challenge. In addition to the handling and inspection challenges comes the board density. Spacing to neighboring components continues to be compressed so the rework techniques should not damage neighboring components.
Technical Library | 2010-07-15 19:19:56.0
When reworking more complex SMT components such as finer pitch SMT components, SMTconnectors and even area array devices, the most common method of printing on the printing selectively on the PCB has some serious shortcomings. The most significant problem
Technical Library | 2013-07-03 10:31:54.0
It has been demonstrated in numerous pieces of work that stencil printing, one of the most complex PCB assembly processes, is one of the largest contributors to defects (Revelino et el). This complexity extends to prototype builds where a small number of boards need to be assembled quickly and reliably. Stencil printing is becoming increasingly challenging as packages shrink in size, increase in lead count and require closer lead spacing (finer pitch). Prototype SMT assembly can be further divided between industrial and commercial work and the DIYer, hobbyist or researcher groups. This second group is highly price sensitive when it comes to the materials used for the board assembly as their funds are sourced from personal or research monies as opposed to company funds. This has led to development of a lower cost SMT printing stencil made from plastic film as opposed to the more traditional stainless steel stencil used by industrial and commercial users.This study compares the performance of these two traditional materials and their respective impact on solder paste printing including efficiency and print quality.
Technical Library | 2023-07-25 16:50:02.0
Some of the new handheld communication devices offer real challenges to the paste printing process. Normally, there are very small devices like 01005 chip components as well as 0.3 mm pitch uBGA along with other devices that require higher deposits of solder paste. Surface mount connectors or RF shields with coplanarity issues fall into this category. Aperture sizes for the small devices require a stencil thickness in the 50 to 75 um (2-3 mils) range for effective paste transfer whereas the RF shield and SMT connector would like at least 150 um (6 mils) paste height. Spacing is too small to use normal step stencils. This paper will explore a different type of step stencil for this application; a "Two-Print Stencil Process" step stencil. Here is a brief description of a "Two-Print Stencil Process". A 50 to 75 um (2-3 mils) stencil is used to print solder paste for the 01005, 0.3 mm pitch uBGA and other fine pitch components. While this paste is still wet a second in-line stencil printer is used to print all other components using a second thicker stencil. This second stencil has relief pockets on the contact side of the stencil any paste was printed with the first stencil. Design guidelines for minimum keep-out distances between the relief step, the fine pitch apertures, and the RF Shields apertures as well relief pocket height clearance of the paste printed by the first print stencil will be provided.
Technical Library | 2017-09-28 16:36:33.0
These nano-coatings also refine the solder paste brick shape giving improved print definition. These two benefits combine to help the solder paste printing process produce an adequate amount of solder paste in the correct position on the circuit board pads. Today, stencil aperture area ratios from 0.66 down to 0.40 are commonly used and make paste printing a challenge. This paper presents data on small area ratio printing for component designs including 01005 Imperial (0402 metric) and smaller 03015 metric and 0201 metric chip components and 0.3 mm and 0.4 mm pitch micro BGAs.
Technical Library | 2015-05-14 15:45:45.0
The Printed Circuit Board industry has seen a steady reduction in pitch from 1.0mm to 0.4mm; a segment of the industry is even using or considering a 0.25mm pitch. This has increased the use of stacked microvias in these designs. The process of stacking microvias has been practiced for several years in handheld devices; however, the devices generally do not operate in harsh conditions. Type 1 and Type 2 microvias have been tested over the years and have been found to be very reliable. We do not have enough test data for 3 and 4 stack microvias when placed on and off buried via. The main objective of this study was to understand the reliability of 3 and 4 stack microvias placed on and off a buried via.
Technical Library | 2013-03-14 17:19:28.0
Commercial-off-the-shelf ball/column grid array packaging (COTS BGA/CGA) technologies in high reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. Understanding the process and quality assurance (QA) indicators for reliability are important for low-risk insertion of these advanced electronic packages. This talk briefly discusses an overview of packaging trends for area array packages from wire bond to flip-chip ball grid array (FCBGA) as well as column grid array (CGA). It then presents test data including manufacturing and assembly board-level reliability for FCBGA packages with 1704 I/Os and 1-mm pitch, fine pitch BGA (FPBGA) with 432 I/Os and 0.4-mm pitch, and PBGA with 676 I/Os and 1.0-mm pitch packages. First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2021-07-13 19:59:34.0
We have investigated the processing of lead-zirconate-titanate-based thick films by inkjet printing Pb (Zr0.53Ti0.47)0.98Nb0.02O3 with a 6 mol% excess of PbO nanosized powder dispersed in water. Differentwaveforms were employed to determine the optimum size and shape of the drops. A uniform, defect-free pattern with dimensions of 4 mm × 4 mm can be printed using 20 V and a drop spacing of 20 μm. The inkjet-printed films were heated to 400 °C to remove the organics and subsequently sintered at 750 and 850 °C. The correlations between the density, grain size and electromechanical properties of the thick films and bulk ceramics are qualitatively discussed. A thickness coupling factor of 46% was obtained for a 15-μm-thick film sintered at low temperature of 850 °C, which is comparable to the value of the bulk ceramic with an identical nominal chemical composition. Our results are important for the economic and environmental-benign printing of piezoelectric materials applicable in variety of electronic devices, such as sensors, actuators, transformers, piezoelectric energy harvesters and transducers.
Technical Library | 2015-12-31 15:19:28.0
Today's consumer electronic product are characterized by miniatuization, portability and light weight with high performance, especially for 3G mobile products. In the future more fine pitch CSPs (0.4mm) component will be required. However, the product reliability has been a big challenge with the fine pitch CSP. Firstly, the fine pitch CSPs are with smaller solder balls of 0.25mm diameter or even smaller. The small solder ball and pad size do weaken the solder connection and the adhesion of the pad and substrate, thus the pad will peel off easily from the PCB substrate. In addition, miniature solder joint reduce the strength during mechanical vibration, thermal shock, fatigue failure, etc. Secondly, applying sufficient solder paste evenly on the small pad of the CSP is difficult because stencil opening is only 0.25mm or less. This issue can be solved using the high end type of stencil such as Electroforming which will increase the cost.
Technical Library | 2010-03-25 06:26:37.0
The complexity of Printed Circuit Assembly process is increasing day by day and causing productivity issues in the industry, introducing ultra fine pitch components (pitch less than 15mil) in PCA is a challenge to minimize risk of defects as solder short, dry solder. This paper is focusing on minimizing these defects.
