Technical Library | 1999-05-07 08:50:40.0
To enable transistor scaling into the 21st century, new solutions such as high dielectric constaConventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10mm in the 1970’s to a present day size of 0.1mm. To enable transistor scaling into the 21st century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be developed. In this paper, for the first time, key scaling limits are quantified for MOS transistorsnt materials for gate insulation and shallow, ultra low resistivity junctions need to be developed.
Technical Library | 2021-09-08 13:57:37.0
While the presence of silver in SAC solder provided excellent temperature cycling durability, the silver in high silver SAC alloy also made the solders susceptible to failures under drop/shock loading. To improve the drop/shock reliability, the silver content in SAC alloys was reduced from three percent, to as low as no silver. Solder dopants, also known as microalloy additions, are elements (typically 0.1% or lower) other than the main constituents of the alloy that have been shown to improve solder performance. Commonly used microalloy additions include nickel (Ni), bismuth (Bi), manganese (Mn), and antimony (Sb).
Technical Library | 2008-08-14 20:48:12.0
The Restriction of Hazardous Substances (RoHS) regulations of the European Union, and similar regulations being enacted around the world, require the virtual elimination of lead (Pb), mercury (Hg), cadmium (Cd), hexavalent chromium (Cr6), polybrominated biphenyls (PBB) or polybrominated diphenyl ethers (PBDE) from electronic products. Allowable concentration levels in any homogeneous material contained within a product are extremely low: 0.01% for Cd and 0.1% for other substances by weight. The most significant issue affecting the practical validation of RoHS compliance in the day-to-day assembly environment is ensuring that no restricted substances, especially tin-lead (SnPb) materials, have inadvertently entered into the production stream.
Technical Library | 2019-01-20 22:47:35.0
With the rapid development of the electronics industry, more and more components such as integrated circuits and connectors, relays, power modules, etc. need to be packaged with IC tubes. The anti static ic tubes is actually a kind of pvc plastic(reference to : What are the materials for IC tubes) profile, the size varies with the shape of the installed product, the precision requirement is high, the wall thickness should be controlled within ±0.1mm, and the surface is required to have no impurity spots, smooth and transparent. The IC packaging tubes produced by Sewate Technology Co., Ltd. are extruded. The typical process flow is: extrusion, vacuum adsorption setting, traction, fixed length cutting and directional discharge, deburring, immersion antistatic liquid, drying, testing, packaging and storage
Technical Library | 2021-10-20 18:21:06.0
The solderability of the SAC305 alloy in contact with printed circuit boards (PCB) having different surface finishes was examined using the wetting balance method. The study was performed at a temperature of 260 _C on three types of PCBs covered with (1) hot air solder leveling (HASL LF), (2) electroless nickel immersion gold (ENIG), and (3) organic surface protectant (OSP), organic finish, all on Cu substrates and two types of fluxes (EF2202 and RF800). The results showed that the PCB substrate surface finish has a strong effect on the value of both the wetting time t0 and the contact angle h. The shortest wetting time was noted for the OSP finish (t0 = 0.6 s with EF2202 flux and t0 = 0.98 s with RF800 flux), while the ENIG finish showed the longest wetting time (t0 = 1.36 s with EF2202 flux and t0 = 1.55 s with RF800 flux). The h values calculated from the wetting balance tests were as follows: the lowest h of 45_ was formed on HASL LF (EF2202 flux), the highest h of 63_ was noted on the OSP finish, while on the ENIG finish, it was 58_ (EF2202 flux). After the solderability tests, the interface characterization of cross-sectional samples was performed by means of scanning electron microscopy coupled with energy dispersive spectroscopy.
Technical Library | 2020-12-24 02:50:56.0
A method for packaging integrated circuit silicon die in thin flexible circuits has been investigated that enables circuits to be subsequently integrated within textile yarns. This paper presents an investigation into the required materials and component dimensions in order to maximize the reliability of the packaging method. Two die sizes of 3.5 mm×8 mm× 0.53 mm and 2 mm×2 mm×0.1 mm have been simulated and evaluated experimentally under shear load and during bending. The shear and bending experimental results show good agreement with the simulation results and verify the simulated optimal thickness of the adhesive layer. Three underfill adhesives (EP30AO, EP37-3FLF, and Epo-Tek 301 2fl), three highly flexible adhesives (Loctite 4860, Loctite 480, and Loctite 4902), and three substrates (Kapton,Mylar, and PEEK) have been evaluated, and the optimal thickness of each is found. The Kapton substrate, together with the EP37-3FLF adhesive, was identified as the best materials combination with the optimum underfill and substrate thickness identified as 0.05 mm.
Technical Library | 2024-04-29 21:39:52.0
In this paper, we develop and put into practice an Automatic Optical Inspection (AOI) system based on machine vision to check the holes on a printed circuit board (PCB). We incorporate the hardware and software. For the hardware part, we combine a PC, the three-axis positioning system, a lighting device and CCD cameras. For the software part, we utilize image registration, image segmentation, drill numbering, drill contrast, and defect displays to achieve this system. Results indicated that an accuracy of 5µm could be achieved in errors of the PCB holes allowing comparisons to be made. This is significant in inspecting the missing, the multi-hole and the incorrect location of the holes. However, previous work only focusses on one or other feature of the holes. Our research is able to assess multiple features: missing holes, incorrectly located holes and excessive holes. Equally, our results could be displayed as a bar chart and target plot. This has not been achieved before. These displays help users analyze the causes of errors and immediately correct the problems. Additionally, this AOI system is valuable for checking a large number of holes and finding out the defective ones on a PCB. Meanwhile, we apply a 0.1mm image resolution which is better than others used in industry. We set a detecting standard based on 2mm diameter of circles to diagnose the quality of the holes within 10 seconds.
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