Technical Library | 2022-09-25 20:18:33.0
Printed circuit board (PCB) bending and/or flexing is an unavoidable phenomenon that is known to exist and is easily encountered during electronic board assembly processes. PCB bending and/or flexing is the fundamental source of tensile stress induced on the electronic components on the board assembly. For more brittle components, like ceramic-based electronic components, micro-cracks can be induced, which can eventually lead to a fatal failure of the components. For this reason, many standards organizations throughout the world specify the methods under which electronic board assemblies must be tested to ensure their robustness, sometimes as a pre-condition to more rigorous environmental tests such as thermal cycling or thermal shock.
Technical Library | 2009-05-21 13:41:05.0
Failure due to board flex cracks persists as the dominant failure mode in multi-layer ceramic capacitors (MLCC). (...) This paper is intended to show the impact of temperature cycling, high-temperature life tests, and multiple bend exposures to the MLCC with this flexible termination.
Technical Library | 2023-07-04 17:31:22.0
Conformal Coatings are polymeric materials used to protect circuitry, parts, and related components. They are most commonly used to protect printed circuit boards (PCBs) and electronic devices. However, conformal coatings can be applied to a wide variety of materials, including metal, plastic, silicone, ceramics, glass, and even paper. We use the term "substrate" to refer to an object or material that's been coated with a conformal coating.
Technical Library | 2023-11-27 18:19:40.0
This page introduces major causes and countermeasures of solder crack in MLCCs (Multilayer Ceramic Chip Capacitors). Major causes of solder cracks Solder cracks on MLCCs developed from severe usage conditions after going on the market and during manufacturing processes such as soldering. Applications and boards that specially require solder crack countermeasures Solder cracks occur mainly because of thermal fatigue due to thermal shock or temperature cycles or the use of lead-free solder, which is hard and fragile.
Technical Library | 2019-08-15 13:31:52.0
Cracks in ceramic chip capacitors can be introduced at any process step during surface mount assembly. Thermal shock has become a "pat" answer for all of these cracks, but about 75 to 80% originate from other sources. These sources include pick and place machine centering jaws, vacuum pick up bit, board depanelization, unwarping boards after soldering, test fixtures, connector insulation, final assembly, as well as defective components. Each source has a unique signature in the type of crack that it develops so that each can be identified as the source of error.
Technical Library | 2014-08-14 17:58:41.0
High reliability applications for high performance computing, military, medical and industrial applications are driving electronics packaging advancements toward increased functionality with decreasing degrees of size, weight and power (SWaP) The substrate technology selected for the electronics package is a key enabling technology towards achieving SWaP. Standard printed circuit boards (PWBs) utilize dielectric materials containing glass cloth, which can limit circuit density and performance, as well as inhibit the ability to achieve reliable assemblies with bare semiconductor die components. Ceramic substrates often used in lieu of PWBs for chip packaging have disadvantages of weight, marginal electrical performance and reliability as compared to organic technologies. Alternative materials including thin, particle-containing organic substrates, liquid crystal polymer (LCP) and microflex enable SWaP, while overcoming the limitations of PWBs and ceramic. This paper will discuss the use of these alternative organic substrate materials to achieve extreme electronics miniaturization with outstanding electrical performance and high reliability. The effect of substrate type on chip-package interaction and resulting reliability will be discussed. Microflex assemblies to achieve extreme miniaturization and atypical form factors driven by implantable and in vivo medical applications are also shown.
Technical Library | 2022-09-25 20:03:37.0
Cracking remains the major reason of failures in multilayer ceramic capacitors (MLCCs) used in space electronics. Due to a tight quality control of space-grade components, the probability that as manufactured capacitors have cracks is relatively low, and cracking is often occurs during assembly, handling and the following testing of the systems. Majority of capacitors with cracks are revealed during the integration and testing period, but although extremely rarely, defective parts remain undetected and result in failures during the mission. Manual soldering and rework that are often used during low volume production of circuit boards for space aggravate this situation. Although failures of MLCCs are often attributed to the post-manufacturing stresses, in many cases they are due to a combination of certain deviations in the manufacturing processes that result in hidden defects in the parts and excessive stresses during assembly and use. This report gives an overview of design, manufacturing and testing processes of MLCCs focusing on elements related to cracking problems. The existing and new screening and qualification procedures and techniques are briefly described and assessed by their effectiveness in revealing cracks. The capability of different test methods to simulate stresses resulting in cracking, mechanisms of failures in capacitors with cracks, and possible methods of selecting capacitors the most robust to manual soldering stresses are discussed.
Technical Library | 2023-08-04 15:27:30.0
A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.
Technical Library | 2024-04-08 15:46:36.0
A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.
Technical Library | 2023-07-25 16:25:56.0
This paper address two significant applications of stencils in advance packaging field: 1. Ultra-Thin stencils for miniature component (0201m) assembly; 2. Deep Cavity stencils for embedded (open cavity) packaging. As the world of electronics continues to evolve with focus on smaller, lighter, faster, and feature-enhanced high- performing electronic products, so are the requirement for complex stencils to assemble such components. These stencil thicknesses start from less than 25um with apertures as small as 60um (or less). Step stencils are used when varying stencil thicknesses are required to print into cavities or on elevated surfaces or to provide relief for certain features on a board. In the early days of SMT assembly, step stencils were used to reduce the stencil thickness for 25 mil pitch leaded device apertures. Thick metal stencils that have both relief-etch pockets and reservoir step pockets are very useful for paste reservoir printing. Electroform Step-Up Stencils for ceramic BGA's and RF Shields are a good solution to achieve additional solder paste height on the pads of these components as well as providing exceptional paste transfer for smaller components like uBGAs and 0201s. As the components are getting smaller, for example 0201m, or as the available real estate for component placement on a board is getting smaller – finer is the aperture size and the pitch on the stencils. Aggressive distances from step wall to aperture are also required. Ultra-thin stencils with thicknesses in the order of 15um-40um with steps of 15um are used to obtain desired print volumes. Stencils with thickness to this order can be potential tools even to print for RDLs in the package.
